Ferroelectric Memory Capacitor Leakage Path for Idle Data Retention
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Solution Overview
Problem
Ferroelectric memory cells with select devices experience current leakage, leading to unintended voltage differentials across capacitors, which can flip dipoles and erase programmed states due to idle electric fields, compromising non-volatility.
Innovation Solution
Incorporating a parallel current leakage path with lower total resistance than the intrinsic leakage path, using leaker material with specific band gaps and configurations to equalize electrode voltages and minimize electric fields when the memory cell is idle, thereby preventing dipole flipping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a select device is electrically coupled in series with a ferroelectric capacitor, then the memory cell can be addressed and controlled, but current leaks through the select device to adjacent substrate material even when idle, creating voltage differential and electric field that flip dipoles and erase programmed state
Solution Approach 1:
A parallel leakage path is introduced as an intermediary element between the capacitor electrodes. This path includes a resistor and a diode connected in parallel, which acts as a mediator to分流 the leakage current away from the substrate. The diode is oriented to conduct in the reverse direction relative to the select device, providing a controlled path for leakage current that prevents voltage differential buildup across the capacitor during idle states, thereby protecting the stored data while maintaining normal select device operation.
2Object-affected harmful factors
If current leakage path resistance is reduced to prevent voltage drop, then electric field is minimized, but this may increase overall current consumption during operation
Solution Approach 1:
The leakage path incorporates a diode that dynamically adjusts its conductivity based on voltage polarity and magnitude. During idle states with small voltage differentials, the diode remains non-conductive or partially conductive, maintaining high resistance to minimize leakage current. During normal read/write operations with larger voltage swings, the diode becomes fully conductive, providing a low-resistance path that safely dissipates leakage current. This dynamic behavior allows the circuit to adapt its resistance characteristics to operational conditions, minimizing energy loss during both idle and active states.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces current leakage during idle states, maintaining the non-volatility of ferroelectric memory cells by ensuring negligible electric fields within the capacitor insulator material, thus preventing unintended data loss.
Implementation Method 1
Incorporating a parallel current leakage path with lower total resistance than the intrinsic leakage path, using leaker material with specific band gaps and configurations to equalize electrode voltages and minimize electric fields when the memory cell is idle
Data Source
AI summary
A memory cell comprises a capacitor comprising a first capacitor electrode having laterally-spaced walls, a second capacitor electrode comprising a portion above the first capacitor electrode, and capacitor insulator material between the second capacitor electrode and the first capacitor electrode. The capacitor comprises an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the capacitor insulator material. A parallel current leakage path is between the second capacitor electrode and the first capacitor electrode. The parallel current leakage path is circuit-parallel with the intrinsic current leakage path, of lower total resistance than the intrinsic current leakage path, and comprises leaker material that is everywhere laterally-outward of laterally-innermost surfaces of the laterally-spaced walls of the first capacitor electrode. Other embodiments, including methods, are disclosed.