Semiconductor Memory Capacitor Contact Silicide Uniformity
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Solution Overview
Problem
As semiconductor devices, such as DRAM, continue to miniaturize, challenges arise due to the small contact area between semiconductor and metal plugs, leading to high capacitance values and non-uniformity of the silicide layer at corners, which affects device performance and reliability.
Innovation Solution
The semiconductor memory structure incorporates a dielectric liner with multiple nitride and oxide layers, and a capacitor contact with a metal silicide liner that extends along both the sidewall and bottom of the metal plug, along with a nitride layer on the silicide liner, to improve contact uniformity and reduce resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device dimensions are continuously shrinked to increase device density, then device density is improved, but contact area between semiconductor plug and metal plug becomes small leading to high capacitance values
Solution Approach 1:
The patent introduces a dielectric liner structure that extends in the vertical dimension (height direction) to provide additional capacitance control. The dielectric liner includes multiple layers (first nitride liner, oxide liner, second nitride liner) stacked vertically around the bit line, creating a three-dimensional capacitance management structure that compensates for the reduced horizontal contact area caused by device miniaturization.
2Reliability
If polysilicon is annealed to form silicide layer, then electrical conductivity is improved, but stress and growth temperature variations cause non-uniformity at corners
Solution Approach 1:
The patent introduces a dielectric liner as an intermediary structure between the polysilicon and the surrounding environment. This dielectric liner acts as a protective and stabilizing medium during the annealing process, providing uniform stress distribution and consistent thermal conditions that enable uniform silicide layer formation even at corner regions where stress concentration typically occurs.
3Productivity
If device dimensions are shrinked to improve performance, then performance is improved, but contact area reduction leads to high resistance
Solution Approach 1:
The patent extends the contact structure into the vertical dimension by incorporating a dielectric liner with multiple stacked layers around the bit line. This vertical extension provides additional contact area and reduces contact resistance without increasing the horizontal footprint, thereby maintaining high device density while improving electrical connectivity.
Data Source
AI summary
A semiconductor memory structure includes a semiconductor substrate, a bit line disposed on the semiconductor substrate, a dielectric liner disposed on a sidewall of the bit line and a capacitor contact disposed on a side of the bit line. The dielectric liner includes a first nitride liner disposed on a sidewall of the bit line, an oxide liner disposed on a sidewall of the first nitride liner, and a second nitride liner disposed on a sidewall of the oxide liner. The capacitor contact includes a semiconductor plug disposed on the semiconductor substrate, a metal plug disposed on the semiconductor plug, a metal silicide liner including a sidewall portion and a bottom portion extending along the sidewall and the bottom of the metal plug respectively, and a nitride layer disposed on the metal silicide liner. The sidewall portion is disposed directly above the second nitride liner.