3D Memory Capacitor Trench Stack for Higher Density Reliability
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Solution Overview
Problem
The integration and reliability of semiconductor devices are limited by the area occupied by unit memory cells, and existing three-dimensional semiconductor devices face challenges in enhancing operation reliability and storage capacity.
Innovation Solution
A semiconductor device with a stack structure including alternately stacked sacrificial and insulating layers, conductive and dielectric layers within trenches, and interconnection structures to connect capacitors in parallel, along with a method of manufacturing that forms trench structures and conductive layers to increase capacitance and storage capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If three-dimensional semiconductor devices with stacked memory cells are used to improve integration density, then the degree of integration is improved, but operation reliability deteriorates
Solution Approach 1:
The device is divided into multiple functional layers including stack structures with alternating sacrificial and insulating layers, gate structures, and capacitor structures with conductive and dielectric layers. This segmentation allows each layer to be optimized independently for both integration density and reliability, resolving the contradiction between high integration and operational stability
Solution Approach 2:
The patent transitions from planar two-dimensional memory cell structures to three-dimensional vertically stacked structures. By stacking multiple memory cells and capacitors in the vertical dimension, the device achieves higher integration density while maintaining reliability through proper structural design and material selection in each dimensional layer
2Productivity
If unit memory cell area is reduced to increase integration density, then the degree of integration is improved, but manufacturing precision requirements increase
Solution Approach 1:
By moving to three-dimensional stacked structures, the patent reduces the lateral footprint of each memory cell while maintaining manufacturability. The vertical stacking allows smaller unit cell area without proportionally increasing manufacturing precision requirements, as the stacking process can be controlled through standardized layer deposition and bonding techniques
Solution Approach 2:
Sacrificial layers are formed in advance during the stack structure fabrication process, enabling subsequent capacitor structures to be precisely positioned and formed within defined spaces. This preliminary formation of structural guides and templates simplifies later manufacturing steps and maintains precision requirements at manageable levels
3Quantity of substance
If capacitor structures with multiple conductive and dielectric layers are formed within trenches to increase capacitance, then storage capacity is improved, but device complexity increases
Solution Approach 1:
The stack structure with alternating sacrificial and insulating layers serves multiple functions: it provides mechanical support, defines trench geometries for capacitor formation, and enables precise positioning of conductive and dielectric layers. This multi-functionality reduces overall device complexity by consolidating multiple structural roles into a single integrated stack architecture
Solution Approach 2:
Capacitor structures with nested conductive and dielectric layers are formed within trenches defined by the stack structure. The conductive layers and dielectric layers are alternately stacked within the trench space, creating a compact nested arrangement that increases capacitance and storage capacity while efficiently utilizing the available volume without proportionally increasing device complexity
Data Source
AI summary
A semiconductor device may include a first semiconductor structure including a gate structure and a stack, the gate structure including channel structures and the stack including a capacitor, and a second semiconductor structure that is bonded to the first semiconductor structure, the second semiconductor structure including a peripheral circuit. The capacitor may include conductive layers and dielectric layers that are alternately stacked along an internal surface of a trench that is formed within the stack.