Memory Capacity Measurement Using Defect Address Mapping

The patent segments the memory device into usable and unusable regions by recording defective memory addresses in a separate defect storage area. This allows the functional portions to be utilized while isolating defects, resolving the contradiction by maintaining reliability through defect isolation while preserving manufacturing precision through selective usage of functional circuits.

The patent applies local quality by treating different memory regions differently - defective regions are marked and excluded while functional regions are preserved and utilized. The defect storage mechanism locally records only the unusable addresses, allowing the majority of functional memory to be used, thus improving manufacturing precision without compromising overall reliability.

By segmenting the memory space into usable and unusable regions through defect address recording, the patent enables utilization of all functional memory circuits. This resolves the contradiction by maintaining reliability through defect isolation while maximizing storage capacity through comprehensive utilization of functional regions.

The patent discards only the minimal necessary defective portions by recording their addresses, while recovering and utilizing the majority of functional memory circuits. This approach maintains device reliability by excluding defective regions while maximizing storage capacity through recovery and use of functional circuits that would otherwise be wasted in conventional downgrading.

The patent implements preliminary action by pre-recording defective memory addresses in the defect storage area during manufacturing or initialization. This allows precise identification of functional circuits to be established beforehand, enabling the memory controller to efficiently manage usable capacity without adding complex real-time measurement mechanisms, thus improving manufacturing precision while controlling device complexity.

The patent introduces an intermediary defect storage mechanism that bridges the gap between raw memory circuits and the memory controller. This intermediary structure stores defect information in a standardized format, allowing the controller to precisely identify functional circuits without direct complex interaction with individual memory cells, thus improving manufacturing precision while managing device complexity through abstraction.

By pre-recording defect information during manufacturing, the patent enables efficient memory utilization from the outset. This preliminary action allows the memory device to achieve high productivity through increased yield without requiring complex real-time measurement and adaptation mechanisms, thus balancing productivity improvement with controlled device complexity.

The patent implements self-service by enabling the memory device to automatically manage its own capacity through internal defect recording and capacity determination mechanisms. The memory controller autonomously calculates usable capacity based on stored defect information, eliminating the need for external complex measurement systems and achieving high productivity through self-managed efficient memory utilization while keeping device complexity manageable.