Non-Volatile Memory Cell Array With Differential Sensing Circuit
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Solution Overview
Problem
Conventional erasable programmable non-volatile memory cells face challenges in maintaining high read current differences between programmed and erased states due to variations in semiconductor manufacturing processes and operating temperatures, leading to impaired applications as the size of memory cells increases, which affects layout area and functionality.
Innovation Solution
The design incorporates a memory array with a first array region of general memory cells and a second array region of reference memory cells, where the read current in the programmed state of general memory cells is higher than that of reference memory cells, and the erase efficiency of general memory cells is superior, utilizing a sensing circuit with a switch set and current comparator to differentiate between programmed and erased states based on read currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the size of memory cells is increased, then the read current difference between programmed and erased states is improved, but the layout area is worsened
Solution Approach 1:
The patent introduces reference memory cells with different characteristics (lower read current, higher erase efficiency) alongside general memory cells. By creating local variations in cell characteristics and using differential sensing, the system achieves reliable state differentiation without requiring increased memory cell size, thus resolving the contradiction between read current difference and layout area.
2Ease of manufacture
If conventional memory cell structures are used, then manufacturing simplicity is maintained, but the ability to maintain high read current differences under process and temperature variations is worsened
Solution Approach 1:
The patent implements a sensing circuit that uses reference memory cells to establish a reference current level. The differential sensing mechanism compares the read current from general memory cells against this reference, providing feedback-based compensation for process and temperature variations. This allows the system to maintain stable read current differences without complicating the manufacturing process.
3Productivity
If general memory cell design is used, then erase efficiency is improved, but differentiation reliability under variations is worsened
Solution Approach 1:
The patent segments the memory array into two distinct types of memory cells: general memory cells optimized for high erase efficiency and reference memory cells optimized for providing stable reference current levels. This segmentation allows each cell type to be independently optimized for its specific function, enabling the system to achieve both high erase efficiency and reliable state differentiation despite process and temperature variations.
Data Source
AI summary
An erasable programmable non-volatile memory includes a memory array and a sensing circuit. The memory array includes a general memory cell and a reference memory cell, which are connected with a word line. The sensing circuit includes a current comparator. The read current in the program state of the general memory cell is higher than the read current in the program state of the reference memory cell. The erase efficiency of the general memory cell is higher than the erase efficiency of the reference memory cell. When a read action is performed, the general memory cell generates a read current to the current comparator, and the reference memory cell generates a reference current to the current comparator. According to the reference current and the read current, the current comparator generates an output data signal to indicate a storage state of the general memory cell.