Computing-in-Memory Cell Array for In-Place Bit-Line Counting
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Solution Overview
Problem
The exponential growth of data generation outpaces data processing capabilities, leading to high time and power costs associated with accessing and processing data, as existing technologies are not optimized for simultaneous high-speed, power-efficient large-scale data access and processing.
Innovation Solution
A memory device with an array of gated computing cells that allows simultaneous access and computation on data stored in memory cells, using logic elements like NOR, OR, AND, and NAND gates to generate signals on a bit line, enabling efficient counting of '1' values without external processing, thereby reducing power consumption and increasing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is accessed and processed using external processing units, then data processing capability is improved, but time cost and power consumption increase
Solution Approach 1:
The patent merges memory storage and processing functions into a single integrated structure by placing logic elements (NAND, NOR, OR, AND gates) directly within memory cells. This allows data to be processed in-place without external processing units, simultaneously improving processing capability while reducing time cost through eliminated data transfer operations.
Solution Approach 2:
The memory cells are designed to perform multiple functions: storing data and executing logical operations. Each memory cell contains both storage elements and logic elements, enabling the same structure to serve as both memory and processor, thereby improving productivity without the overhead of separate processing units.
2Productivity
If data is accessed and processed using external processing units, then data processing capability is improved, but power consumption increases
Solution Approach 1:
By combining storage and processing in the same location, the patent eliminates the energy-consuming data transfer between memory and external processors. The logic elements operate directly on stored data within the memory cell, reducing power consumption while maintaining processing capability.
3Ease of operation
If traditional memory access methods are used, then simplicity is maintained, but speed and efficiency decrease
Solution Approach 1:
The integration of logic elements within memory cells enables parallel processing operations across multiple data elements simultaneously. This maintains the simplicity of memory access interfaces while dramatically improving speed through in-place computational operations that eliminate data movement bottlenecks.
Data Source
AI summary
Systems and methods are provided for a computing-in memory circuit that includes a bit line and a plurality of computing cells connected to the bit line. Each of the plurality of computing cells includes a memory element, having a data output terminal; a logic element, having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the data output terminal of the memory element, the second input terminal receives a select signal; and a capacitor, having a first terminal and a second terminal, where the first terminal is coupled to the output terminal of the logic element, the second terminal is coupled to the bit line. A voltage of the bit line is driven by the plurality of computing cells.