Vertical Memory Cell Charge Trap Segmentation
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Solution Overview
Problem
In highly scaled vertical-type memory devices, the increased cell stack density leads to reduced gaps between adjacent cells, causing charge diffusion and deteriorating the reliability of integrated circuit devices due to cell interference.
Innovation Solution
The integration of conductive patterns, insulating layers, channel layers, charge trap patterns, and blocking dielectric patterns in a specific configuration within the channel holes of the integrated circuit device, including dummy charge trap patterns and blocking dielectric patterns, to minimize cell interference and enhance reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If cell stack density in the vertical direction is increased, then memory capacity is improved, but gap between adjacent cells is reduced causing charge diffusion and reliability deterioration
Solution Approach 1:
The charge storage layer is segmented into multiple distinct charge storage patterns (first charge storage pattern, second charge storage pattern, third charge storage pattern) separated by blocking insulating patterns. This segmentation prevents charge diffusion between adjacent cells while maintaining high vertical stacking density, thus preserving both memory capacity and reliability
Solution Approach 2:
Blocking insulating patterns are introduced as intermediary elements between adjacent charge storage patterns. These blocking patterns act as barriers that prevent charge diffusion while allowing the cells to remain in close vertical proximity, enabling high density without compromising reliability
2Productivity
If gap between adjacent cells is reduced to increase cell stack density, then memory capacity is improved, but cell interference due to charge diffusion increases
Solution Approach 1:
The charge storage layer is divided into multiple segmented charge storage patterns separated by blocking insulating patterns. This segmentation allows cells to be stacked closely together (high productivity) while the blocking patterns prevent charge diffusion (reducing harmful interference)
Solution Approach 2:
The harmful charge diffusion is extracted or removed from the system by introducing blocking insulating patterns that selectively block charge movement between cells while allowing the desired charge storage function to continue
Data Source
AI summary
An integrated circuit device includes a channel layer in a channel hole penetrating a conductive line and an insulating layer, a charge trap pattern inside the channel hole between the conductive line and the channel layer, and a dummy charge trap pattern inside the channel hole between the insulating layer and the channel layer. In order to manufacture the integrated circuit device, a channel hole penetrating an insulating layer and a mold layer is formed. A mold indent connected to the channel hole is formed. A preliminary dielectric pattern is formed in the mold indent. The preliminary dielectric pattern is oxidized to form a first blocking dielectric pattern. A charge trap layer is formed in the channel hole. The mold layer is removed to form a conductive space. A portion of the charge trap layer is removed to form charge trap patterns and dummy charge trap patterns.