Semiconductor Memory Cell Layout for CMP Flatness Control
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Solution Overview
Problem
The challenge in semiconductor manufacturing is controlling the flatness of underlying layers during lithography operations due to height differences caused by non-volatile memory cells and peripheral devices, which affect chemical mechanical polishing (CMP) performance.
Innovation Solution
A method is introduced where the substrate in the non-volatile memory cell area is etched to create a step, reducing height differences, and the substrate surface for high-voltage areas is recessed to minimize the impact of thick gate dielectric layers on CMP operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If non-volatile memory cells and peripheral devices are formed on the substrate, then device functionality is achieved, but height differences are created that affect lithography and CMP operations
Solution Approach 1:
The substrate is selectively recessed in specific regions (non-volatile memory cell area and high-voltage circuit area) while maintaining the original surface level in other areas. This creates locally adapted surface profiles that accommodate different device requirements without affecting overall device functionality.
Solution Approach 2:
The invention addresses the height difference problem by modifying the substrate surface in the vertical dimension, creating stepped surface levels. This dimensional approach allows different device areas to have optimized surface heights for their specific operations while maintaining horizontal integration.
2Manufacturing precision
If the substrate surface is recessed to reduce height differences, then CMP performance is improved, but additional manufacturing steps are required
Solution Approach 1:
The substrate recessing operation is performed before subsequent lithography and CMP operations. This preliminary action pre-establishes the optimal surface profile, allowing later processes to proceed without the complications of height differences that would otherwise require additional corrective steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the performance of CMP by reducing height differences and improving planarization, thereby improving the manufacturing process efficiency and device performance.
Implementation Method 1
the substrate in the non-volatile memory cell area is etched to create a step
Implementation Method 2
chemical mechanical polishing operations have played an important role for planarizing the underlying layer
Data Source
AI summary
In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.