Semiconductor Memory Cell Layout for CMP Planarization
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in controlling the flatness of underlying layers during lithography operations, particularly due to height differences caused by stacked structures in non-volatile memory cells and peripheral circuits, which affect chemical mechanical polishing (CMP) performance.
Innovation Solution
A method is introduced to form a step between non-volatile memory (NVM) cell and peripheral device areas, adjusting the substrate surface levels to minimize height differences, and forming gate dielectric layers with varying thicknesses to accommodate different operational voltages, thereby improving CMP performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If stacked structures are used to increase device density, then device density is improved, but height differences between areas increase causing CMP performance degradation
Solution Approach 1:
The patent applies local quality by forming different thicknesses of gate dielectric layers in different circuit areas based on their specific operational requirements. High-voltage circuits receive thicker gate dielectric layers while low-voltage circuits receive thinner layers, allowing each area to have optimized electrical properties while maintaining overall planarization compatibility for CMP processes.
2Adaptability or versatility
If gate dielectric layers with varying thicknesses are formed to accommodate different operational voltages, then adaptability is improved, but height differences between areas increase affecting CMP performance
Solution Approach 1:
The patent implements local quality by tailoring gate dielectric layer thickness to the specific voltage requirements of each circuit area. This allows high-voltage circuits to have thicker insulation layers while low-voltage circuits have thinner layers, optimizing electrical performance for each region while the overall structure remains compatible with CMP planarization processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces height discrepancies, enhancing the effectiveness of CMP and ensuring consistent planarization across areas with varying gate dielectric thicknesses, thus improving semiconductor device performance.
Implementation Method 1
chemical mechanical polishing operations have played an important role for planarizing the underlying layer
Data Source
AI summary
In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.