Memory Cell Contact Layout for Dense DRAM Reliability

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Solution Overview

Problem

As semiconductor devices become more highly integrated, the miniaturization of individual circuit patterns poses challenges in maintaining electrical characteristics and reliability, particularly in semiconductor memory devices with complex contact structures.

Innovation Solution

The semiconductor memory device incorporates specific contact structures, including bit line contacts, node pads, and storage contacts with unique geometries and materials to enhance electrical connectivity and reduce contact resistance, featuring non-overlapping side surfaces and varying widths to improve reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If contact structures are miniaturized to increase integration density, then device integration is improved, but electrical characteristics and reliability deteriorate

Engineering Contradiction:

Improveintegration densityVSAvoidelectrical characteristics

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The storage contact is designed with a nested structure where the first part is positioned within the horizontal projection area of the bit line spacer, creating a compact nested arrangement that saves space while maintaining electrical performance

Inventive Principle:

Principle #7Nested doll (Nesting)

Solution Approach 2:

The storage contact transitions from a simple planar contact to a three-dimensional structure with varying width (first part wider than second part), utilizing vertical and horizontal dimensions to increase contact area without expanding the device footprint

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Reliability

If contact area is increased to reduce resistance, then electrical characteristics are improved, but device area increases

Engineering Contradiction:

Improveelectrical characteristicsVSAvoiddevice area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The storage contact has non-uniform width distribution with the first part having a larger width than the second part, concentrating the contact area increase in the critical region near the bit line spacer where resistance reduction is most needed

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The storage contact's first part is nested within the horizontal projection area of the bit line spacer, allowing the contact area to be increased without proportionally increasing the overall device area

Inventive Principle:

Principle #7Nested doll (Nesting)

Data Source

PatentUS12550316B2Semiconductor memory device

Publication Date: 2026.02.10 SAMSUNG ELECTRONICS CO LTD

AI summary

Provided is a semiconductor memory device comprising an active region extending in a cell isolation layer, wherein the active region includes a first region and a second region; a bit line intersects the active region; a bit line contact between a substrate and the bit line, wherein the bit line contact is electrically connected to the first region; a bit line spacer that is on side surfaces of the bit line and the bit line contact; a node pad on a lateral side of the bit line spacer, wherein the node pad is electrically connected to the second region; a storage contact that is on the node pad and on a side surface of the bit line spacer, wherein the storage contact includes a first part having a first width and a second part having a second width different from the first width.