Memory Cell Diode Configuration for Low Line Resistance
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Solution Overview
Problem
The 2D/1R memory cell array architecture experiences low set and reset currents due to high resistance in the bit and reset lines, limiting its performance.
Innovation Solution
The memory cell design includes a first diode with an N-type doped region connected to a bit line and a second diode with a P-type doped region connected to a reset line, both on a semiconductor substrate, with isolation structures to reduce line resistance and increase current flow, using a data storage material layer between electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the n-well of the first diode is used as a bit line and the p-well of the second diode is used as a reset line in the 2D/1R array architecture, then the array density and working current are improved, but the set current and reset current become small
Solution Approach 1:
The patent divides the bit line and reset line into separate dedicated lines instead of using the well regions directly as lines. This segmentation allows independent optimization of each line's resistance and current-carrying capacity, resolving the contradiction between high density and sufficient current.
Solution Approach 2:
The patent introduces intermediate connection structures (metal contacts and interconnect lines) between the diodes and the bit/reset lines. These intermediaries provide low-resistance pathways that enable high current flow while maintaining the compact 2D/1R architecture.
2Device complexity
If the n-well and p-well are used directly as bit and reset lines, then the device complexity is reduced, but the line resistance increases
Solution Approach 1:
The patent changes the resistance parameter of the bit and reset lines by using heavily doped semiconductor regions and metal interconnects instead of lightly doped well regions. This parameter change reduces line resistance while maintaining the simplicity of the overall device structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the resistance of the bit and reset lines, thereby increasing the set and reset currents, enhancing the array's operational efficiency.
Implementation Method 1
PN junction is formed at the interface between the P+ doped region and the n-well. The second diode of the two diodes includes an N+ doped region and a p-well. PN junction is formed at the interface between the N+ doped region and a p-well.
Implementation Method 2
Problems arise, however, the set current and the reset current of the 2D/1R array architecture described above are small. Therefore, there is a need to provide array architecture of a 2D/1R in which the reset current and the reset current may be increased.
Data Source
AI summary
Semiconductor devices and fabrication methods thereof are provided to form a memory cell. The memory cell includes a first diode, a second diode separated from the first diode. The first diode includes a first well region in a substrate, a first N-type doped region adjacent to the first well region and connected to a bit line, and a first P-type doped region adjacent to the first well region and separated from the first N-type doped region. The second diode includes a second well region in the substrate, a second N-type doped region adjacent to the second well region, and a second P-type doped region. The memory cell further includes a bottom electrode connected to the first P-type doped region and the second N-type doped region, respectively, a top electrode connected to a word line, and a data storage material layer located between the bottom electrode and the top electrode.