3D Memory Cell Electrode Structure for Higher Density Storage
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Solution Overview
Problem
Existing semiconductor technologies face challenges in increasing memory cell density and reducing parasitic capacitance in three-dimensional memory devices.
Innovation Solution
A semiconductor device with a vertical conductive line, horizontal layer, and data storage element featuring a merged double cylinder structure is fabricated, including a first and second horizontal portion and a dual work function horizontal conductive line, to enhance memory cell integration and storage capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a conventional single cylinder structure is used for data storage, then the manufacturing process is simpler, but the memory cell density and storage capacity are limited
Solution Approach 1:
The patent merges two separate cylinder structures into a single integrated first electrode, forming a merged double cylinder structure that includes a first cylinder and a second cylinder. This merging approach increases the storage capacity and memory cell density while maintaining a manageable structural complexity through unified electrode design.
Solution Approach 2:
The patent transitions from a conventional single-cylinder configuration to a merged double cylinder structure that utilizes three-dimensional spatial arrangement. The first and second cylinders are positioned at different locations and orientations, effectively using additional spatial dimensions to increase storage capacity without proportionally increasing manufacturing complexity.
2Quantity of substance
If the cylinder length is increased to improve storage capacity, then more storage space is available, but the parasitic capacitance increases
Solution Approach 1:
The patent segments the first electrode into two separate but merged cylinders (first cylinder and second cylinder) instead of using a single long cylinder. This segmentation allows the storage capacity to be increased through multiple distributed cylindrical structures while reducing the parasitic capacitance that would accumulate in a single extended cylinder structure.
Solution Approach 2:
The patent combines multiple smaller cylinder structures into a merged double cylinder configuration, achieving increased storage capacity through the collective volume of multiple cylinders rather than extending a single cylinder. This merging approach distributes the electrical fields and reduces parasitic capacitance effects compared to a single large cylinder.
3Strength
If a thicker horizontal layer is used, then the structural strength is improved, but the manufacturing precision and electrode alignment become more difficult
Solution Approach 1:
The patent applies different thickness characteristics to different portions of the horizontal layer. The first horizontal portion has a first thickness while the second horizontal portion has a second thickness that is different from the first. This local quality variation allows the structure to maintain sufficient strength where needed while enabling precise electrode alignment in other regions, resolving the contradiction between strength and manufacturing precision.
Data Source
AI summary
A semiconductor device including highly integrated memory cells and a method for fabricating the same. The semiconductor device may include: a vertical conductive line; a horizontal layer horizontally oriented from the vertical conductive line and including a first horizontal portion and a second horizontal portion thinner than the first horizontal portion; a horizontal conductive line crossing the first horizontal portion of the horizontal layer; and a data storage element including a first electrode including a merged double cylinder coupled to the second horizontal portion of the horizontal layer.