Non-volatile Memory Cell Inhibiting Over-erasure
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Solution Overview
Problem
Conventional non-volatile memory cells suffer from over-erasure, where the floating gate becomes positively charged during erasure, leading to programming failures and unpredictable memory states due to production irregularities, and existing solutions either require additional components, increase power consumption, or are ineffective for large-scale memory arrays.
Innovation Solution
A saturating erase operation is performed by applying an elevated erase voltage higher than that causing over-erasure, activating tunneling current to prevent excessive charging of the floating gate, using a method that compensates for electron discharge and injection to maintain optimal erase conditions, reducing over-erasure and improving memory cell reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional erasure voltage is applied to erase the memory cell, then the floating gate is charged, but over-erasure occurs causing programming failures
Solution Approach 1:
The patent applies a compensating voltage to the bit line during the erase operation that acts in opposition to the over-erasure effect. This preliminary anti-action prevents the floating gate from acquiring excessive positive charge by introducing a counterbalancing electrical influence throughout the erase process, thereby maintaining programming capability while achieving thorough erasure.
Solution Approach 2:
The patent modifies the erase operation by introducing an additional voltage parameter (compensating voltage) applied to the bit line. This changes the electrical parameters of the erase process from a single-voltage application to a multi-voltage coordinated application, allowing precise control over the floating gate charge level and preventing over-erasure while maintaining erase effectiveness.
2Reliability
If additional components are added to inhibit over-erasure, then over-erasure is reduced, but device complexity and cost increase
Solution Approach 1:
The patent employs existing memory cell components (bit line, transistor gates, floating gate) to perform the over-erasure inhibition function. The compensating voltage is applied through the existing bit line infrastructure, and the memory cell's own transistor structures are utilized to generate the necessary electrical fields, eliminating the need for additional dedicated components while achieving reliable over-erasure prevention.
Solution Approach 2:
The bit line, traditionally used only for data input/output, is given an additional function of applying compensating voltage during erase operations to prevent over-erasure. This multi-functionality allows the existing component to serve dual purposes: normal data operations and over-erasure inhibition, thereby avoiding increased device complexity while improving reliability.
3Reliability
If individual memory cell erase conditions are optimized, then over-erasure is inhibited, but erase time becomes too long for large-scale arrays
Solution Approach 1:
The patent implements a block-based erase strategy where memory arrays are divided into manageable blocks that are erased in sequential periods. Each block receives the compensating voltage treatment for controlled erasure, and after completion, the next block is processed. This periodic approach maintains reliable over-erasure inhibition while enabling parallel processing of multiple blocks, thereby achieving both reliability and acceptable erase speed for large-scale arrays.
Solution Approach 2:
The patent divides the large-scale memory array into smaller block segments for independent erase operations. This segmentation allows the compensating voltage mechanism to be applied effectively to each block without requiring the entire array to be processed sequentially, thus maintaining the reliability benefits of individual cell optimization while achieving parallel processing efficiency suitable for large-scale arrays.
4Reliability
If larger programming voltage is applied to combat over-erasure, then programming capability is maintained, but power consumption increases
Solution Approach 1:
Instead of increasing the programming voltage to compensate for over-erasure effects, the patent changes the approach by applying a compensating voltage during the erase operation itself. This parameter change in the erase process (rather than the program process) maintains programming capability by preventing excessive positive charge accumulation, while avoiding the power consumption penalty of using higher programming voltages.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The saturating erase operation effectively inhibits over-erasure, enhances programming accuracy, and reduces sensitivity to production irregularities and memory state distributions, allowing for reliable operation in large-scale memory arrays with controlled erase times and reduced power consumption.
Implementation Method 1
activating tunneling current to prevent excessive charging of the floating gate
Data Source
AI summary
A memory cell includes a first transistor and a second transistor. The first transistor is configured as an erase capacitor, and the second transistor is configured as a program transistor. Gates of the first and second transistors are coupled together to form a floating gate. During an erase operation, a first voltage (like 12V-24V) is applied to the first transistor, such as to a source, a body, and a drain of the first transistor. A second voltage (like ground) is applied to the second transistor, such as to a source and a body of the second transistor. A drain of the second transistor could be grounded. The first and second voltages cause electron discharge from the floating gate through the first transistor and electron injection through the second transistor onto the floating gate. This helps to prevent an over-erase condition from forming in the memory cell.