Memory Cell Isolation Structure for Program Disturbance
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Solution Overview
Problem
Non-volatile memory devices face issues with the second bit effect and program disturbance due to reduced channel length and spacing during miniaturization, affecting reliability and performance.
Innovation Solution
A memory cell design with a substrate, doped regions of different conductivity types, stacked structures with charge storage layers, and isolation structures that completely cover the doped regions, effectively blocking electron travel between cells to prevent program disturbance and reduce the second bit effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If memory size is reduced for miniaturization, then memory density is improved, but program disturbance and second bit effect increase
Solution Approach 1:
The patent introduces isolation structures that segment and electrically isolate adjacent memory cells from each other. These isolation structures divide the continuous substrate into isolated regions, preventing electron leakage between neighboring cells while maintaining compact cell dimensions.
Solution Approach 2:
The isolation structures serve as intermediary elements positioned between adjacent memory cells. These intermediaries block the harmful electron flow that causes program disturbance and second bit effect, allowing miniaturization without compromising reliability.
2Length of moving object
If channel length is reduced for miniaturization, then memory density is improved, but second bit effect increases
Solution Approach 1:
The isolation structures segment the channel region electrically, creating isolated conduction paths. This segmentation prevents electrons from one memory cell from interfering with adjacent cells through the substrate, eliminating the second bit effect even with shortened channel lengths.
Solution Approach 2:
The patent extracts and removes the harmful electron flow path by introducing isolation structures that block substrate conduction. This extraction of the harmful electron pathway eliminates the mechanism causing second bit effect while allowing reduced channel length.
3Area of stationary object
If spacing between elements is shortened for miniaturization, then memory density is improved, but program disturbance increases
Solution Approach 1:
The isolation structures create electrical segmentation between closely spaced memory elements. Even though physical spacing is reduced for higher density, the electrical isolation prevents harmful interactions, maintaining reliability despite reduced spacing.
Solution Approach 2:
The isolation structures act as intermediary barriers between closely spaced elements. These intermediaries block electron flow and electric field interference between adjacent cells, preventing program disturbance even when elements are tightly packed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design isolates storage locations within each memory cell, reducing the second bit effect and preventing program disturbance, while integrating with current manufacturing processes without requiring excessive additional steps.
Implementation Method 1
The first isolation structure completely covers and is in contact with the bottom surface of each of the doped regions of the first conductivity type and the bottom surface of the doped region of the second conductivity type
Data Source
AI summary
Provided is a memory cell including a substrate, two doped regions of a first conductivity type, one doped region of a second conductivity type, two stacked structures, and a first isolation structure. The doped regions of the first conductivity type are respectively disposed in the substrate. The doped region of the second conductivity type is disposed in the substrate between the two doped regions of the first conductivity type. The stacked structures are disposed on the substrate and respectively cover the corresponding doped regions of the first conductivity type and a portion of the doped region of the second conductivity type. Each of the stacked structures includes one charge storage layer. The first isolation structure completely covers and is in contact with the bottom surface of each of the doped regions of the first conductivity type and the bottom surface of the doped region of the second conductivity type.