Non-Volatile Memory Cell Isolation Structure for Lower Program-Erase Voltage
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Solution Overview
Problem
Existing erasable programmable non-volatile memory technologies require large layout areas for charge pumps to generate high erase and program voltages, which also stress electronic components and are inefficient.
Innovation Solution
A novel memory cell structure with an isolation area in a semiconductor substrate, where the memory cell operates within the isolation area and receives negative voltages, using diodes to isolate the control circuit, allowing for lower program and erase voltages without affecting the control circuit operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a charge pump is used to generate high erase and program voltages, then the memory cell can perform program and erase operations, but the layout area of the non-volatile memory increases
Solution Approach 1:
The patent divides the semiconductor substrate into distinct regions: a first region for the memory cell and a second region for the control circuit, separated by an isolation structure. This segmentation allows the memory cell to operate with high voltages while the control circuit operates with standard voltages, eliminating the need for a large charge pump and reducing the overall layout area.
Solution Approach 2:
The isolation structure acts as an intermediary between the memory cell and the control circuit. It includes an N-type isolation region that electrically isolates the first P-well region from the P-type semiconductor substrate, enabling different voltage domains to coexist without interfering with each other.
2Reliability
If a charge pump is used to output high erase voltage, then the memory cell can be erased, but the electronic components in the charge pump must withstand high voltage stress
Solution Approach 1:
By segmenting the device into isolated voltage domains, the patent allows the memory cell to experience high voltage stress during erase operations while the control circuit components remain in a low-voltage domain, protecting them from damage.
Solution Approach 2:
The isolation structure serves as a protective intermediary that prevents high voltage stress from the memory cell from affecting the control circuit, eliminating the need for the control circuit components to withstand high voltages.
3Device complexity
If the second gate structure is extended to the second region through the isolation structure, then the memory cell structure is optimized, but the isolation structure must be penetrated
Solution Approach 1:
The isolation structure is formed first as a reference, and then the gate structures are formed to extend through or alongside it. This preliminary formation of the isolation structure guides subsequent manufacturing steps, making the overall process more systematic and controllable.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables efficient program and erase operations with reduced voltage requirements, minimizing the size of the charge pump and protecting the control circuit from voltage stress.
Implementation Method 1
an N-type isolation region, wherein the N-type isolation region is arranged between the first P-well region and the P-type semiconductor substrate to isolate the first P-well region from the P-type semiconductor substrate, the N-type isolation region is arranged between the second P-well region and the P-type semiconductor substrate to isolate the second P-well region from the P-type semiconductor substrate
Implementation Method 2
The storage state of the erasable programmable non-volatile memory cell is determined according to the number of charges stored in the floating gate of the floating gate transistor
Implementation Method 3
when a program action is performed, a program voltage is provided to the memory cell. Consequently, carriers (e.g., electrons) are injected into the floating gate of the floating gate transistor
Implementation Method 4
When an erase action is performed, an erase voltage is provided to the memory cell. Consequently, carriers (e.g., electrons) are ejected from the floating gate of the floating gate transistor
Data Source
AI summary
An erasable programmable non-volatile memory cell includes an isolation structure, a first P-well region, a second P-well region, an N-type isolation region, a first gate structure, a second gate structure, a first merged doped region, a second merged doped region, a third merged doped region and a fourth merged doped region. The isolation structure is formed on a P-type semiconductor substrate. The first gate structure and the second gate structure are formed on the surface of the P-type semiconductor substrate corresponding to the first region. An area the P-type semiconductor substrate corresponding to the first region are divided into a first merged doped region, a second merged doped region and a third merged doped region. The fourth merged doped region is formed in the P-type semiconductor substrate corresponding to the second region.