Shared Memory Cell Logic for Lock-Free Composite Assignment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing systems face challenges in implementing well-defined, flexible computation that allows multiple processors to access a shared memory cell concurrently without conflicts, as they require locking the memory cell for updates, limiting parallel computing efficiency.
Innovation Solution
A novel system with a shared memory architecture that enables multiple processors to perform concurrent composite assignments on a shared memory cell using OR= and AND= operations, where the memory cell is not read before writing, allowing multiple processors to update the memory concurrently without locking, using logical operations integrated within the memory cell.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If locking mechanism is used to ensure exclusive access to memory cell during updates, then data consistency is improved, but parallel processing capability deteriorates
Solution Approach 1:
The memory system is segmented into multiple independently accessible memory cells, each capable of being updated by multiple processors simultaneously without requiring global locking. The segmentation allows parallel composite assignments to proceed independently on different cells while maintaining data consistency within each cell through the commutative and associative properties of the operations.
Solution Approach 2:
The patent introduces a specialized memory cell design with intermediary logic that automatically handles concurrent write operations. The memory cell includes circuitry that detects and resolves conflicts between simultaneous writes from different processors, acting as an intermediary that ensures data consistency without requiring external locking mechanisms.
2Measurement precision
If read operation is performed before write operation on shared memory cell, then data accuracy is improved, but execution time deteriorates
Solution Approach 1:
The memory cell is pre-configured with initialization logic that sets default values before any write operations occur. This preliminary action ensures that when multiple processors perform composite assignments simultaneously, the operations are applied to known initial states, maintaining data accuracy without requiring sequential read-before-write execution.
Solution Approach 2:
Instead of the conventional read-then-write sequence, the patent inverts the approach by allowing direct write operations to proceed simultaneously while relying on the commutative and associative properties of the composite assignment operations. The final state is guaranteed to be correct regardless of execution order, eliminating the need for sequential read operations.
3Productivity
If multiple processors access shared memory cell concurrently, then processing speed is improved, but conflict probability deteriorates
Solution Approach 1:
The patent implements a copying mechanism where each processor works with a local copy of the memory cell state or uses separate buffer registers for concurrent writes. The copies are then merged using composite assignment operations that are guaranteed to produce consistent results regardless of the order of merging, thereby allowing concurrent access without conflicts.
Solution Approach 2:
The memory system changes the operational parameters of the memory cell to support concurrent access. This includes modifying the write logic to accept multiple write signals simultaneously and using parameter transformations that ensure the final state is independent of the sequence of operations, thereby reducing conflict probability while maintaining high processing speed.
Data Source
AI summary
It is an object of the disclosed technique to provide a novel method and system for shared concurrent access to a memory cell. In accordance with the disclosed technique, there is thus provided a system for shared concurrent access to a memory cell, which includes at least one shared memory cell, an evaluator and a plurality of processing agents coupled to the input of the evaluator. The evaluator is further coupled with the at least one memory cell. The evaluator is configured to evaluate an expression for performing multiple concurrent composite assignments on the at least one shared memory cell. The evaluator further allows each of the plurality of processing agents to perform concurrent composite assignments on the at least one shared memory cell. The composite assignments do not include a read operation of the at least one shared memory cell by the plurality of processing agents.