Memory Cell Assemblies with Long-Channel Select Gates
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Solution Overview
Problem
Conventional NAND memory devices face challenges with short-channel effects in drain-side select gates (SGDs), which affect the reliability and performance of memory operations.
Innovation Solution
The development of new methods and architectures for fabricating drain-side select gates (SGDs) using multiple conductive levels to create long-channel SGDs, reducing short-channel effects and enhancing memory cell performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional short-channel SGDs are used in NAND memory devices, then device complexity is reduced and manufacturing is easier, but reliability deteriorates due to short-channel effects
Solution Approach 1:
The SGD is divided into multiple segments (first SGD segment, second SGD segment, third SGD segment) positioned at different vertical locations. Each segment can be independently controlled through separate conductive levels, allowing the structure to achieve long-channel effect mitigation while maintaining manageable complexity through modular design
Solution Approach 2:
The patent transitions from a conventional single-level SGD to a multi-level SGD structure extending vertically through multiple conductive levels (first, second, and third conductive levels). This vertical dimensionality change creates a long-channel effect that improves reliability by preventing unwanted tunneling, while the patent manages the increased complexity through systematic layering and selective removal of sacrificial materials
2Reliability
If multiple conductive levels are used to create long-channel SGDs, then reliability is improved by reducing short-channel effects, but manufacturing complexity increases
Solution Approach 1:
Sacrificial materials are deposited and patterned in advance at specific locations before forming the final conductive structures. The first sacrificial material is removed to form openings for first conductive material, then second sacrificial material is added and removed to create openings for second conductive material, and third sacrificial material is added and removed for third conductive material. This preliminary action approach allows complex multi-level structures to be built through systematic, repeatable steps
Solution Approach 2:
Sacrificial materials serve as intermediary substances that facilitate the formation of the multi-level SGD structure. These materials are temporarily introduced to define the geometry of conductive levels, then systematically removed to leave the desired conductive pathways. This intermediary approach simplifies the manufacturing process by breaking down the complex structure formation into manageable deposition and etching steps
Data Source
AI summary
Some embodiments include an assembly having a stack of alternating dielectric levels and conductive levels. Channel material pillars extend through the stack. Some of the channel material pillars are associated with a first sub-block, and others of the channel material pillars are associated with a second sub-block. Memory cells are along the channel material pillars. An insulative level is over the stack. A select gate configuration is over the insulative level. The select gate configuration includes a first conductive gate structure associated with the first sub-block, and includes a second conductive gate structure associated with the second sub-block. The first and second conductive gate structures are laterally spaced from one another by an intervening insulative region. The first and second conductive gate structures have vertically-spaced conductive regions, and have vertically-extending conductive structures which electrically couple the vertically-spaced conductive regions to one another. Some embodiments include methods of forming assemblies.