Memory Cell Programming with Omitted Pre-Charge and Verify Phases

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Solution Overview

Problem

Existing memory devices face challenges in optimizing programming operations, particularly in reducing damage and increasing the number of program-erase cycles while minimizing program time, especially in single-level cell (SLC) mode, due to data retention issues and program disturb risks.

Innovation Solution

The proposed solution involves omitting the pre-charge and verify phases in the initial program loop of SLC programming, reducing the program pulse magnitude and duration, and incorporating a recovery phase, while maintaining these phases in subsequent loops, and adjusting program pulse magnitude based on the selected word line position to reduce wear and enhance data retention.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the pre-charge and verify phases are included in the initial program loop, then data retention is improved, but program time increases and memory cell damage occurs

Engineering Contradiction:

Improvedata retentionVSAvoidprogram time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent segments the programming operation into distinct phases: an initial program loop without pre-charge and verify phases, followed by additional program loops with these phases. This segmentation allows the system to achieve different objectives in different phases - rapid initial programming followed by verification and correction

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent implements periodic verification and correction by repeating the pre-charge and verify phases in additional program loops after the initial programming phase, allowing iterative improvement of data retention without continuously extending program time

Inventive Principle:

Principle #19Periodic action

2Manufacturing precision

If the pre-charge and verify phases are included in the initial program loop, then programming accuracy is improved, but the number of program-erase cycles decreases

Engineering Contradiction:

Improveprogramming accuracyVSAvoidnumber of program-erase cycles

Core Design Contradiction:

Manufacturing precisionVSReliability

Solution Approach 1:

The patent divides the programming process into an initial aggressive programming phase that achieves basic programming accuracy quickly, followed by additional phases that refine accuracy through verification and correction, thereby reducing overall stress on memory cells

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The initial program loop applies excessive programming voltage without verification to quickly establish the programmed state, accepting some imprecision initially, then subsequent loops apply partial verification to correct errors, reducing the need for repeated full programming cycles

Inventive Principle:

Principle #16Partial or excessive action

3Speed

If the program pulse magnitude is increased, then programming speed is improved, but memory cell damage increases

Engineering Contradiction:

Improveprogramming speedVSAvoidmemory cell damage

Core Design Contradiction:

SpeedVSObject-affected harmful factors

Solution Approach 1:

The patent uses periodic programming pulses with varying magnitudes - high magnitude pulses in the initial loop for fast programming, followed by lower magnitude verification pulses in additional loops to correct errors without causing excessive damage

Inventive Principle:

Principle #19Periodic action

Solution Approach 2:

The patent changes the program pulse magnitude parameter between different program loops - using higher magnitudes initially for speed, then reducing magnitudes in subsequent loops for verification and correction, optimizing the balance between speed and cell stress

Inventive Principle:

Principle #35Parameter changes

4Reliability

If word line position is considered for program pulse adjustment, then wear distribution is improved, but control complexity increases

Engineering Contradiction:

Improvewear distributionVSAvoidcontrol complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies local quality by adjusting program pulse characteristics based on the specific word line position being programmed, recognizing that different word lines experience different stress and require different programming parameters to achieve uniform wear distribution

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent implements dynamic control of program pulse magnitude based on real-time word line position information, allowing the programming parameters to adapt to the specific location being programmed, optimizing wear distribution across the memory array

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS11475957B2Optimized programming with a single bit per memory cell and multiple bits per memory cell

Publication Date: 2022.10.18 SANDISK TECHNOLOGIES LLC

AI summary

Apparatuses and techniques are described for optimizing programming in a memory device in which memory cells can be programmed using single bit per cell programming and multiple bits per cell programming. In one aspect, a single bit per cell program operation is performed which reduces damage to the memory cells as well as reducing program time. The program operation can omit a pre-charge phase and a verify phase of an initial program loop of a program operation. Instead, a program phase is performed followed by a recovery phase. In one or more subsequent program loops of the single bit per cell program operation, as well as in each program loop of a multiple bit per cell program operation, the program loop includes a pre-charge phase, a program phase, a recovery phase and a verify phase.