Memory Cell Programming with Verify-Guided Pulse Acceleration
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Solution Overview
Problem
Existing memory devices face challenges in efficiently programming memory cells to achieve optimal threshold voltage distributions, particularly when transitioning between adjacent data states, leading to prolonged program times due to the need for numerous incremental voltage pulses.
Innovation Solution
Implementing a verify operation to confirm successful programming of adjacent data states and applying a larger program pulse, combined with an offset voltage, to accelerate the programming process by reducing the number of required pulses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If incremental step pulse programming is used to program memory cells, then programming precision and threshold voltage distribution are improved, but program time is significantly increased due to the need for numerous incremental voltage pulses
Solution Approach 1:
The patent performs verify operations at intermediate stages during the programming process to check whether memory cells have reached expected threshold voltage levels. By detecting programming status early and using this information to adjust subsequent pulse parameters, the system avoids unnecessary incremental pulses and reduces overall program time while maintaining precision
Solution Approach 2:
The patent implements verify operations that provide feedback on the programming status of memory cells. Based on the verify results, the control logic dynamically adjusts programming parameters such as pulse width and voltage levels. This feedback mechanism allows the system to stop incremental pulsing once sufficient programming is achieved, significantly reducing program time while maintaining threshold voltage distribution precision
2Measurement precision
If multiple verify operations are performed to confirm programming of adjacent data states, then programming accuracy is improved, but device complexity and operation time are increased
Solution Approach 1:
The patent combines multiple verify operations for adjacent data states into a unified verify sequence. Instead of performing separate verify operations for each data state transition, the system uses a single verify operation that checks multiple states simultaneously or uses the verify result of one state to inform the verification of adjacent states, thereby reducing overall complexity while maintaining accuracy
3Productivity
If a larger program pulse is applied after verify operation to accelerate programming, then programming speed is improved, but risk of over-programming and threshold voltage distribution deviation increases
Solution Approach 1:
The patent dynamically adjusts program pulse parameters based on real-time verify operation results. When verify operations indicate that memory cells are接近 the target threshold voltage, the system reduces pulse width or voltage levels to avoid over-programming. This dynamic adjustment mechanism allows the system to maintain precision while accelerating programming through optimized pulse sequences
Solution Approach 2:
The patent applies program pulses that may slightly exceed the minimum required for programming, followed by verify operations to check for over-programming. If verify operations detect excessive threshold voltage shifts, the system compensates by reducing subsequent pulse magnitudes. This approach allows for accelerated programming while maintaining precision through corrective feedback
Data Source
AI summary
The present disclosure discloses a memory device, a program method, and a memory system. The memory device includes: a memory cell array and a peripheral circuit configured to: apply a verify voltage to a word line when incremental step pulse programming is performed on a plurality of memory cells, so as to perform a first verify operation on a first data state among the plurality of data states and perform a second verify operation on a second data state among the plurality of data states, wherein the first data state is adjacent to the second data state, and a distance between a first expected threshold voltage distribution corresponding to the first data state and a second expected threshold voltage distribution corresponding to the second data state is greater than a preset threshold; wherein the second program pulse is a previous program pulse of the first program pulse.