Floating-Gate Memory Cell with Separate Read Path Reliability
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Solution Overview
Problem
Existing memory cells are large in size, suffer from high voltage stress, and have poor reading reliability due to the use of floating gate transistors, which adversely affect read reliability and endurance.
Innovation Solution
The memory cell design includes a first transistor with a floating gate terminal connected to a second transistor, and a third transistor for read operations, separated from the erase/program path, using a common well region to reduce size and separate read and program paths, and employs a core device for read operations to mitigate high-voltage stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If floating gate transistors are used for memory cell operations, then non-volatile storage capability is achieved, but read reliability deteriorates due to high voltage stress and transistor degradation
Solution Approach 1:
The patent segments the memory cell operations into separate paths: a first transistor handles erase/program operations while a second transistor handles read operations. This segmentation allows read operations to be performed through a dedicated path that does not involve the floating gate transistor, thereby avoiding high voltage stress during reads and improving read reliability.
Solution Approach 2:
The patent introduces a third transistor as an intermediary element that couples the first and second transistors. This intermediary allows the read current to flow through the second transistor without directly stressing the floating gate transistor, while still enabling control over the memory cell state through the first transistor's programming operations.
2Duration of action of stationary object
If floating gate transistors are used for memory operations, then non-volatile storage is achieved, but transistor degradation increases reducing endurance
Solution Approach 1:
The patent divides the transistor functions into separate devices: the first transistor (with floating gate) handles only erase/program operations, while the second transistor handles read operations. This segmentation prevents the floating gate transistor from experiencing repeated read stresses that would cause degradation, thereby improving overall endurance.
Solution Approach 2:
The patent extracts the read operation function from the floating gate transistor and assigns it to a separate second transistor. This extraction removes the harmful read-related stress from the floating gate transistor, allowing it to focus only on programming operations where it is less susceptible to degradation.
3Reliability
If separate read and program paths are implemented, then read reliability is improved, but device complexity increases
Solution Approach 1:
The patent merges the functionality of multiple transistors into a compact three-transistor configuration. The first transistor handles program/erase, the second handles reads, and the third acts as a coupling device. This merging approach achieves separate read and program paths while minimizing the total transistor count compared to fully independent paths.
Solution Approach 2:
The third transistor serves multiple functions: it couples the first and second transistors, enables control line signaling, and facilitates both read and program operations through its strategic positioning. This multi-functionality reduces the need for additional dedicated transistors for each operation type.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves size reduction, improved endurance, and low-voltage read operations with enhanced read reliability and current sensing window, while suppressing transistor degradation.
Implementation Method 1
When a program operation is performed on the memory cell, a plurality of electrons are injected from the body terminal of the first transistor into the gate terminal of the first transistor
Data Source
AI summary
A memory cell includes a first transistor, a second transistor, and a third transistor. A body terminal of the first transistor is connected to an erase line. A first source/drain terminal of the first transistor is connected to a program line. Body terminals of the second transistor and the third transistor are connected to a control line. A first source/drain terminal of the second transistor is connected to a bit line. A gate terminal of the second transistor is connected to a gate terminal of the first transistor. A first source/drain terminal of the third transistor is connected to the control line. A second source/drain terminal of the third transistor is connected to a second source/drain terminal of the second transistor. A gate terminal of the third transistor is connected to a word line. The gate terminals of the first transistor and second transistor are floating.