Memory Cell Low Voltage Read Current Segmentation
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Solution Overview
Problem
Existing memory cell technologies face challenges in reading data efficiently under low voltage conditions due to significant decay of read current along long charging paths, leading to increased time for data retrieval.
Innovation Solution
The memory cell design incorporates a programming selection transistor, a following gate transistor, an antifuse varactor, and a reading circuit with specific voltage control signals and transistor configurations to form a stable read current, including a reading transistor and a reading selection transistor to manage parasitic capacitance and reduce unintentional triggering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the memory cell operates with low voltage, then power consumption is reduced, but the read current becomes too small and decays significantly along the column, increasing reading time
Solution Approach 1:
The memory cell is segmented into multiple transistors (first transistor, second transistor, third transistor, fourth transistor) with specific coupling relationships. The second transistor is coupled to the third transistor, and the fourth transistor is coupled to both the first and third transistors, creating a segmented current path that reduces the impact of parasitic capacitance and enables low-voltage operation with sufficient read current.
Solution Approach 2:
The third transistor acts as an intermediary element between the antifuse transistor and the bit line. This intermediate transistor amplifies and transfers the read current more effectively, compensating for the decay caused by parasitic capacitance in the column, thereby enabling reliable low-voltage operation.
2Reliability
If the read current charges parasitic capacitors along the column, then data can be read, but the long charging path causes significant decay and increases reading time
Solution Approach 1:
The read current path is segmented through multiple transistors, with the second transistor coupled to the third transistor and the fourth transistor coupled to both the first and third transistors. This segmentation creates multiple current paths that can charge parasitic capacitors more efficiently, reducing the overall charging time and decay effects.
Solution Approach 2:
The memory cell uses a composite transistor configuration combining NMOS and PMOS transistors in specific arrangements. The fourth transistor is coupled to both the first and third transistors, creating a composite structure that provides both high current drive capability and low voltage operation, effectively charging parasitic capacitors faster.
Data Source
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AI summary
A memory cell includes a programming selection transistor, a following gate transistor, an antifuse element, and a reading circuit. A charging current formed by the antifuse element may trigger the reading circuit to form a stable read current during a reading operation of the memory cell so that the time for reading data from the memory cell is shortened. A discharging process may be operated in the beginning of the reading operation of the memory cell so that the window of time for reading data from the memory cell can be widened.