3D Memory Cell Repair Using Chalcogenide Active Area Switching
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Solution Overview
Problem
Existing memory technologies face challenges in enhancing data storage reliability and durability, particularly in addressing failed memory cells and ensuring efficient data storage operations.
Innovation Solution
The proposed solution involves a memory cell array design with vertically stacked word planes and bit lines, utilizing a chalcogenide-based memory material layer that changes threshold voltage levels based on current direction, and a repair mechanism for failed cells through forming new active areas using controlled voltage applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a memory cell array is designed with vertically stacked word planes and bit lines to increase storage capacity, then the data storage reliability and durability are improved, but the device complexity increases
Solution Approach 1:
The memory cell array is divided into multiple word planes (first word plane, second word plane, etc.) that are vertically stacked. Each word plane contains memory cells formed between bit lines and word line electrodes, allowing independent operation and repair of each plane. This segmentation enables the system to maintain reliability by isolating failures to specific planes while preserving the overall high-capacity structure.
Solution Approach 2:
The patent transitions from a planar memory structure to a three-dimensional vertically stacked architecture. Multiple word planes are arranged in the vertical dimension, with bit lines penetrating through all planes. This dimensional change increases storage capacity without proportionally increasing planar area, thereby improving reliability through redundancy while managing device complexity through vertical integration.
2Reliability
If a repair mechanism is implemented for failed memory cells by forming new active areas, then the data storage reliability is improved, but the operating procedure complexity increases
Solution Approach 1:
The repair mechanism performs preliminary actions by first identifying failed memory cells through error detection, then preparing the repair process by selecting appropriate bit lines and word planes. The system accumulates error information and determines fail cells before executing the repair operation, which involves applying voltages to form new active areas. This preliminary preparation simplifies the overall repair procedure by planning the restoration sequence in advance.
Solution Approach 2:
The repair process utilizes parameter changes by applying different voltage levels to bit lines and word planes to induce formation of new active areas in failed memory cells. By controlling voltage parameters (first voltage, second voltage, third voltage) during the repair operation, the system transforms the electrical characteristics of failed cells to restore their functionality, thereby improving reliability through controlled parameter manipulation rather than complex structural changes.
3Reliability
If error detection and correction mechanisms are implemented to identify and repair failed cells, then the data integrity is improved, but the processing time increases
Solution Approach 1:
The system implements feedback mechanisms by continuously monitoring memory cell operations for errors, accumulating error information, and using this feedback to identify fail cells. The controller receives data from memory apparatuses, corrects errors, and tracks error locations. This feedback loop enables timely detection and repair of failed cells, improving data integrity while minimizing processing time by addressing errors as they occur rather than through lengthy post-processing.
Solution Approach 2:
The memory system performs self-service through autonomous error detection and repair capabilities. The controller automatically identifies failed cells, selects appropriate repair operations, and executes voltage applications to form new active areas without external intervention. This self-service approach improves data integrity by continuously maintaining memory health while reducing processing time compared to manual error correction methods.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances data storage reliability and durability by enabling effective repair of failed cells and improving data storage operations, ensuring consistent performance and data integrity.
Implementation Method 1
utilizing a chalcogenide-based memory material layer that changes threshold voltage levels based on current direction
Implementation Method 2
forming new active areas using controlled voltage applications
Data Source
AI summary
A memory system may include a memory apparatus including a memory cell array in which active areas of each pair of adjacent memory cells are formed to face each other, the memory cell array including a plurality of memory cells, a controller that controls the memory apparatus, and a buffer memory that stores data received from the controller and provides the stored data to the controller.