Memory Cell Reset Circuit for Read Disturb Error Correction
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Solution Overview
Problem
Memory cells in semiconductor devices experience read disturb effects, leading to data loss and failed read operations, especially under process voltage temperature (PVT) conditions such as higher read voltage levels and operation temperatures.
Innovation Solution
A semiconductor device configuration that includes a memory circuit, an error correction code circuit, a logic circuit, a register circuit, and a write circuit. The error correction code circuit detects read disturb errors and generates error information, which activates the write circuit to reset memory cells using pulse signals with controlled voltage levels and durations, thereby correcting errors without damaging the memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If higher read voltage levels are used to improve read operation speed, then read speed is improved, but read disturb effect increases causing data loss
Solution Approach 1:
The patent applies preliminary action by performing a reset operation on memory cells before read operations. The reset circuit resets memory cells that may have been affected by previous read disturb effects, ensuring they are in a known good state before the actual read operation. This preventive measure eliminates the need to use excessively high read voltages, thus maintaining both fast read speed and data integrity.
2Productivity
If higher operation temperatures are used to improve device performance, then device performance is improved, but read disturb effect increases causing read operation failures
Solution Approach 1:
The reset circuit performs preliminary reset operations on memory cells before read operations, especially under high temperature conditions. This preliminary action compensates for the increased read disturb effect at higher temperatures, ensuring memory cells are in a reliable state for read operations without sacrificing device performance.
3Reliability
If read voltage levels are reduced to minimize read disturb effect, then data integrity is improved, but read operation speed decreases
Solution Approach 1:
By performing reset operations before read operations, the patent ensures memory cells are in a known good state. This allows the use of lower, safer read voltages that minimize read disturb effects while maintaining adequate read speeds, because the preliminary reset has already prepared the memory cells for reliable reading.
4Reliability
If reset operations are performed frequently to correct read disturb errors, then data integrity is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent introduces a dedicated reset circuit as an intermediary component between the memory array and the read/write circuits. This specialized reset circuit is designed to work cooperatively with the existing memory structure, providing error correction functionality without requiring complete redesign of the memory architecture, thus limiting the increase in device complexity.
Data Source
AI summary
A semiconductor device includes an error correction code circuit and a register circuit. The error correction code circuit is configured to generate first data according to second data. The register circuit is configured to generate reset information according to a difference between the first data and the second data, for adjusting a memory cell associated with the second data. A method is also disclosed herein.