Memory Cell Re-Verification for Tighter Threshold Voltage Distributions
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Solution Overview
Problem
Existing memory devices face challenges in achieving tight threshold voltage distributions due to phenomena like CELSRC bounce, which leads to increased threshold voltage distribution widths and reduced reliability of programmed data.
Innovation Solution
A programming technique that includes multiple program loops with verify operations, locking out memory cells that pass initial verify, followed by re-verification to correct any cells that mistakenly passed due to CELSRC bounce, and adjusting program pulse voltage incrementally until all cells meet the desired threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If memory cells are programmed using conventional verify operations, then programming speed is improved, but threshold voltage distribution width increases due to CELSRC bounce
Solution Approach 1:
The patent implements a feedback mechanism by performing re-verify operations after initial programming and verify steps. The system uses the verify result to determine whether additional programming is needed, creating a closed-loop control system that adjusts programming based on actual threshold voltage achievement, thereby tightening the distribution width while maintaining programming speed.
Solution Approach 2:
The patent applies preliminary action by performing an initial programming step followed by a verify operation before finalizing the programming state. This preliminary verification allows the system to identify and correct cells that may have mistakenly passed due to CELSRC bounce, ensuring more accurate threshold voltage distribution before completing the programming process.
2Reliability
If verify operations are performed to ensure accurate threshold voltage, then reliability is improved, but programming time increases
Solution Approach 1:
The patent applies partial action by performing verify operations selectively based on the verify pass/fail count. When the count indicates sufficient reliability (below threshold), additional re-verify operations are skipped, reducing unnecessary programming time. This approach ensures data reliability while avoiding excessive verification that would extend programming time unnecessarily.
Solution Approach 2:
The patent implements dynamic programming by adjusting the number of re-verify operations based on real-time verify pass/fail counts. The system dynamically determines whether to perform additional programming and verify cycles based on the observed distribution width and reliability metrics, optimizing the balance between reliability and programming time for each specific programming scenario.
3Measurement precision
If re-verify operations are performed on all memory cells, then threshold voltage precision is improved, but device complexity increases
Solution Approach 1:
The patent applies local quality by performing re-verify operations selectively on specific memory cells based on their verify results, rather than uniformly on all cells. The system identifies cells that failed initial verify or have threshold voltages near the target value and applies additional programming and re-verify only to these specific cells, reducing overall operational complexity while maintaining high measurement precision for the critical subset.
Solution Approach 2:
The patent segments the programming process into distinct phases: initial programming, first verify, conditional re-verify, and final programming. By dividing the process into manageable segments with clear decision points based on verify pass/fail counts, the system improves threshold voltage measurement precision through structured re-verification while keeping device complexity manageable through systematic process organization.
Data Source
AI summary
The memory device includes a memory block with memory cells arranged in word lines and control circuitry that is configured to program the memory cells in a selected word line to respective programmed data states in program loops, which each include verify operations. The control circuitry is further configured to lock out any of the memory cells in the selected word line memory cell from subsequent program pulses and verify operations in response to that memory cell passing verify for its respective programmed data state. For a selected programmed data state, the control circuitry is further configured to re-verify all of the memory cells in the selected word line that are being programmed to the selected programmed data state and release all memory cells that were locked out but fail re-verify in order to allow any memory cells that mistakenly passed verify to be programmed further.