Nonvolatile Memory Cell Segmentation for Write Speed and Disturb
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Solution Overview
Problem
In nonvolatile memory cells, increasing the drain voltage for faster write speeds leads to a 'disturb phenomenon' where electrons are injected into unselected cells, making it difficult to discriminate between selected and unselected memory cells, especially in downsized memory cell arrays.
Innovation Solution
A nonvolatile memory cell configuration with a first n-well, a second n-well, and a floating gate electrode that overlaps with both, where voltages are applied to the drain and gate of the selected cell and the second n-well to enhance write speed while minimizing interference with unselected cells, using a specific structure and voltage application to differentiate between selected and unselected cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the drain voltage is increased to achieve faster write speed, then the write speed is improved, but a disturb phenomenon occurs in unselected memory cells making it difficult to discriminate between selected and unselected cells
Solution Approach 1:
The invention divides the n-well structure into two separate n-wells (first n-well and second n-well) positioned at different locations. The floating gate electrode overlaps with both n-wells, creating distinct regions for selected and unselected cell control. This segmentation allows independent voltage application to each n-well, enabling the selected cell to receive high drain voltage for fast writing while unselected cells maintain lower voltages to avoid disturb phenomena.
Solution Approach 2:
The invention applies different voltage conditions to different spatial locations within the memory cell structure. By applying high drain voltage only to the selected cell's drain region and specific gate voltages to the floating gate electrode, the write operation is localized to the selected cell. Unselected cells experience different voltage conditions that prevent electron injection, thus maintaining discrimination reliability even when selected cells operate at high speeds.
2Quantity of substance
If the memory cell array is downsized to increase density, then the storage capacity is improved, but the disturb phenomenon becomes more severe and discrimination between cells becomes more difficult
Solution Approach 1:
By segmenting the n-well into two distinct n-wells with a floating gate overlapping both, the invention creates a more refined control structure that works effectively in downsized arrays. This segmented architecture maintains clear electrical isolation between selected and unselected cells even when cell dimensions are reduced, preventing the spread of disturb phenomena in high-density configurations.
Solution Approach 2:
The invention utilizes the vertical dimension by having the floating gate electrode overlap with both the first and second n-wells in a three-dimensional arrangement. This vertical stacking and overlapping configuration allows for better spatial separation and control of electrical fields, enabling reliable cell discrimination in downsized arrays where lateral separation is limited.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for faster write speeds in selected nonvolatile memory cells while maintaining high reliability and performance by effectively distinguishing between selected and unselected cells, even in densely packed arrays.
Implementation Method 1
a state in which electrons are injected in the floating gate electrode is defined as a written state
Implementation Method 2
stored data is erased by means of applying a positive voltage to the second n-well and emitting electrons of the floating gate electrode to the second n-well
Implementation Method 3
a nonvolatile memory cell is configured with a first well having a conductivity type of an n-type, a second well having a conductivity type of the n-type, formed at a position different from the position of the first well, a transistor formed in the first well
Data Source
AI summary
A semiconductor device including a nonvolatile memory cell with a high performance and also a high reliability is provided. A nonvolatile memory cell includes a first n-well, a second n-well separated from the first n-well in a first direction, a selection transistor formed in the first n-well, a floating gate electrode formed to overlap with a part of the first n-well and a part of the second n-well in a plan view, and an n-conductivity-type semiconductor regions formed in the second n-well on both sides of the floating gate electrode. In write operation, −7 V is applied to the drain of a selected nonvolatile memory cell, −8 V is applied to the gate electrode of the selection transistor, and further −3 V is applied to the n-conductivity-type semiconductor region for obtaining a higher write speed. Thereby, a selected nonvolatile memory cell is discriminated from an unselected nonvolatile memory cell.