Non-volatile Memory Cell Threshold Voltage Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In multi-valued non-volatile semiconductor memory devices, the rising threshold voltage distribution caused by capacitive coupling interference between memory cells leads to difficulties in faithfully storing data, as the interval between adjacent voltage levels becomes narrow, making it challenging to accurately perform write-in and read-out operations.
Innovation Solution
A non-volatile semiconductor memory device with a control circuit that selects an adjacent word line to perform a write-in operation using an erasing level weaker than the data write-in level, and verifies soft programming of one page, thereby achieving a narrow-banded erasing level distribution, which minimizes the shift in threshold voltage and reduces error possibilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a write-in operation is performed on a memory cell using high voltage to inject electrons into the floating gate, then the threshold voltage rises to store data, but the threshold voltage distribution of adjacent memory cells also rises due to capacitive coupling interference, narrowing the interval between adjacent voltage levels
Solution Approach 1:
The patent applies preliminary anti-action by performing a compensatory write-in operation on adjacent memory cells before the threshold voltage distribution becomes problematic. When a write-in operation is performed on a target memory cell, the control circuit subsequently performs another write-in operation on adjacent memory cells at a lower voltage level to counteract the capacitive coupling interference that would otherwise cause unwanted threshold voltage shifts in the adjacent cells.
Solution Approach 2:
The patent utilizes parameter changes by adjusting the voltage level applied during the compensatory write-in operation. The control circuit applies a lower voltage level to adjacent memory cells compared to the target memory cell, creating a controlled threshold voltage shift that compensates for the capacitive coupling effect and maintains uniform threshold voltage distribution across the memory array.
2Adaptability or versatility
If threshold voltages are widely distributed to provide multi-values in memory cells, then more data values can be stored, but the interval between adjacent level voltage values becomes narrow, making it difficult to faithfully store and read data
Solution Approach 1:
The patent implements feedback by having the control circuit monitor and verify the threshold voltage distribution after write-in operations. The control circuit performs verify operations to check whether the threshold voltages of memory cells fall within expected ranges, and based on this feedback, adjusts subsequent write-in operations to maintain proper voltage level separation and ensure accurate data storage and retrieval.
3Productivity
If a high voltage is applied to perform a write-in operation on a target memory cell, then electrons are injected into the floating gate to change the threshold voltage, but this causes a shift in threshold voltage of surrounding memory cells due to electric field interference
Solution Approach 1:
The patent uses an intermediary approach by introducing a compensatory operation as a mediator between the target write-in operation and adjacent memory cells. The control circuit performs an additional write-in operation on adjacent cells at a reduced voltage level, which acts as an intermediary action to offset the harmful electric field effects and maintain overall threshold voltage uniformity across the memory array.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively limits the rise in threshold voltage during write-in operations, ensuring a uniform shift and maintaining a sufficient window between threshold voltage distributions, thereby alleviating error possibilities in write-in and read-out operations.
Implementation Method 1
the rising threshold voltage distribution caused by capacitive coupling interference between memory cells
Data Source
AI summary
A non-volatile semiconductor memory device, comprising: a non-volatile memory array, storing multi-values by setting a plurality of different threshold voltages for each memory cell, and a control circuit, controlling a write-in operation to the memory cell array. When data have been written into the memory cell, the control circuit selects an adjacent word line, uses an erasing level to perform write-in which is weaker than the data write-in, and verifies soft programming of the amount of one page, such that a narrow-banded erasing level distribution is realized in an adjacent memory cell.