Memory Cell Programming with Two-Stage Threshold Convergence
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Solution Overview
Problem
Existing memory programming operations require a large number of programming voltage pulses to achieve desired threshold voltage distributions, affecting timing and efficiency.
Innovation Solution
Implementing a two-stage programming process, using all-level programming (ALP) in stage one to position threshold voltage distributions near verify levels, followed by selective slow program convergence (SSPC or ASSPC) in stage two to compact distributions and achieve desired parameters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional single-stage programming is used, then programming completeness is achieved, but the number of pulses required is large and timing is poor
Solution Approach 1:
The programming operation is divided into two distinct stages: Stage 1 (All-Level Programming) that positions all programming levels simultaneously, and Stage 2 (Selective Slow Program Convergence) that compacts threshold voltage distributions. This segmentation allows each stage to optimize for its specific function, reducing the total number of pulses required compared to traditional single-stage programming.
Solution Approach 2:
Stage 1 performs preliminary positioning of all programming levels to approximate their target distributions before Stage 2 performs the final compacting. By preparing the threshold voltage distributions in advance with rough positioning, the second stage requires fewer pulses to achieve the final precise distribution, thereby reducing overall programming time.
2Manufacturing precision
If more programming pulses are applied, then threshold voltage distribution precision is improved, but programming time increases
Solution Approach 1:
The programming process is segmented into two functional stages: Stage 1 positions all programming levels to approximate target distributions, and Stage 2 performs selective compacting to achieve final precision. This segmentation allows the system to achieve high threshold voltage distribution precision with fewer total pulses by dividing the precision achievement into two phases rather than requiring one long phase.
Solution Approach 2:
The patent changes programming parameters dynamically between stages: Stage 1 uses programming parameters optimized for positioning multiple levels simultaneously, while Stage 2 uses different parameters optimized for compacting specific level distributions. This parameter optimization for each stage reduces the total pulse count needed to achieve the desired precision.
3Measurement precision
If programming levels are positioned precisely, then data accuracy is improved, but the complexity of control increases
Solution Approach 1:
The control process is segmented into two distinct phases with different control objectives: Stage 1 controls all programming levels simultaneously to approximate positions, while Stage 2 selectively controls specific levels for compacting. This segmentation simplifies the control logic compared to attempting to precisely control all levels in a single stage, as each stage has a focused control goal.
Solution Approach 2:
Stage 1 performs preliminary positioning of all programming levels to approximate their target distributions before Stage 2 performs the final precise compacting. This preliminary action reduces the control complexity of Stage 2, as the levels are already near their target positions and only require fine-tuned compacting rather than full-positioning control.
Data Source
AI summary
Systems and methods for two-stage memory cell programming. An example memory device comprises: a memory array; and a controller coupled to the memory array, the controller to perform operations comprising: receiving a request to perform a memory programming operation with respect to a target set of memory cells electrically coupled to a target wordline and a set of target bitlines; performing a first stage of the memory programming operation by causing a ramping up programming voltage to be applied to the target wordline while causing one or more pillars associated with the target memory cells to be boosted in a staggered manner; and performing a second stage of the memory programming operation by causing a programming voltage to be applied to the target wordline, while selectively applying bias voltage to the set of target bitlines.