Memory Cell Well Layout for Plural-Bit Soft Error Isolation
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Solution Overview
Problem
Existing cell-based design for semiconductor circuits faces challenges in reducing plural-bit soft errors due to the propagation of charge-induced errors across shared N and P wells, leading to performance drops and potential circuit failures, as conventional methods like increasing transistor size or distance between latches result in increased power consumption and circuit size, and the use of dummy wells complicates manufacturing and separation.
Innovation Solution
The proposed solution involves arranging N and P wells in a perpendicular direction between adjacent memory cells, forming continuous well regions that are isolated by wells of opposite conductivity type, creating a barrier to prevent charge propagation and reducing the size requirements for individual wells, allowing for efficient error suppression without modifying existing standard cell designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the distance between adjacent latches is increased to reduce soft errors, then the probability of charge propagation decreases, but the circuit size increases
Solution Approach 1:
The patent divides the continuous well structure into isolated segments by inserting dummy wells between adjacent latches. This segmentation prevents charge propagation across the entire well while maintaining compact latch spacing, thereby reducing soft errors without increasing circuit size.
Solution Approach 2:
Dummy wells are introduced as intermediary structures between adjacent latches. These dummy wells act as barriers that block charge propagation while occupying minimal space, enabling soft error reduction without requiring increased distance between functional latches.
2Reliability
If the size of transistors is increased to reduce soft errors, then the critical charge amount increases, but the power consumption increases
Solution Approach 1:
The patent segments the well structure using dummy wells to prevent charge propagation. This allows the use of smaller transistors with lower critical charge requirements while maintaining soft error tolerance through physical isolation, thereby reducing power consumption.
3Reliability
If dummy wells are inserted between adjacent latches to prevent charge propagation, then soft error reduction is achieved, but the manufacturing complexity increases
Solution Approach 1:
The patent merges the dummy well structures with the existing N-well and P-well formation processes. By integrating dummy wells into the standard CMOS well fabrication sequence, the manufacturing complexity is minimized while achieving charge propagation prevention.
4Ease of operation
If the N well and P well are formed in parallel to the cell-placement row, then standard cell placement is simplified, but charge can propagate between adjacent cells
Solution Approach 1:
The patent maintains the parallel well orientation for ease of cell placement but introduces dummy wells to segment the continuous well structure. This segmentation creates electrical isolation between adjacent cells while preserving the simplified placement methodology.
Solution Approach 2:
Dummy wells are inserted as intermediary structures between adjacent standard cells. These intermediaries block charge propagation paths while maintaining the parallel well configuration that enables simple cell placement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces the occurrence of plural-bit soft errors by creating a depleted layer around well borders, preventing electron and hole propagation between wells, thus enhancing radiation tolerance without increasing power consumption or circuit size, and allowing for the use of existing standard cells.
Implementation Method 1
This configuration effectively reduces the occurrence of plural-bit soft errors by creating a depleted layer around well borders, preventing electron and hole propagation between wells
Data Source
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AI summary
A semiconductor integrated circuit includes a plurality of memory cells (30) arranged in a cell-placement row (31) extending in a first direction (X), a first N well (34) and a first P well (35) arranged in a second direction (Y) perpendicular to the first direction in each area of the memory cells, and a second N well (36) and a second P well (37) each having the same length as a width of the cell-placement row and situated between at least two adjacent memory cells of the plurality of memory cells, wherein the first N well and the second N well are integrated, and the first P well and the second P well are integrated.