Non-volatile Multilevel Memory Cells Programming Sequence
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Solution Overview
Problem
As NAND flash memory scales, parasitic capacitance coupling between adjacent memory cell floating gates leads to floating gate-to-floating gate interference, causing wider threshold voltage distributions and degraded programming performance, especially in multi-level cell devices where threshold voltage differences are small.
Innovation Solution
Assigning different numbers of program states to cells based on a programming sequence, where cells programmed earlier have fewer states and those programmed later have more, to reduce interference effects and maintain storage capacity while minimizing adverse floating gate-to-floating gate interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If NAND flash memory is scaled to increase memory density, then storage capacity is improved, but parasitic capacitance coupling between adjacent floating gates increases causing threshold voltage distribution to widen and programming performance to degrade
Solution Approach 1:
The patent segments the programming process into multiple sequential phases, where different subsets of memory cells are programmed at different times. This temporal segmentation reduces simultaneous interference between adjacent floating gates during programming operations, thereby maintaining tighter threshold voltage distributions even as memory density increases through scaling.
Solution Approach 2:
The patent applies preliminary actions by pre-programming certain memory cells before others in a controlled sequence. By establishing a programming hierarchy where some cells are programmed first and others later, the system mitigates the adverse effects of parasitic capacitance coupling that would otherwise occur if all cells were programmed simultaneously at scaled dimensions.
2Quantity of substance
If multiple level cell (MLC) architecture is used to store multiple bits per cell, then storage capacity is improved, but floating gate-to-floating gate interference is greatly increased due to small threshold voltage differences
Solution Approach 1:
The patent segments the memory cell array into different programming groups that are programmed at different times. This segmentation allows MLC cells to be programmed in a controlled sequence, reducing the simultaneous interference effects that would otherwise be magnified by the small threshold voltage differences between multiple storage levels.
Solution Approach 2:
The patent implements preliminary programming actions for specific cell subsets before programming other cells. This preliminary action approach allows the system to establish certain threshold voltage states first, then subsequently program adjacent cells with reduced interference, which is critical for maintaining the integrity of multiple closely-spaced threshold levels in MLC architecture.
3Productivity
If all memory cells are programmed simultaneously to maximize programming speed, then productivity is improved, but floating gate interference causes erroneous data reads and degraded reliability
Solution Approach 1:
The patent divides the memory cell population into multiple programmable subsets that can be processed in parallel but at different times. This segmentation enables a form of pipelined programming where different groups are programmed sequentially, maintaining high overall productivity while ensuring that interference-induced errors are minimized within each subset.
Solution Approach 2:
The patent applies preliminary programming to specific cell subsets before proceeding to other subsets. This preliminary action ensures that cells programmed earlier establish their threshold voltage states before adjacent cells are programmed, thereby preventing interference from causing erroneous programming or read errors while maintaining efficient overall programming throughput.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces erroneous data reads and maintains or increases storage capacity by providing larger read margins for cells programmed first and smaller margins for cells programmed later, effectively mitigating the effects of floating gate-to-floating gate interference.
Implementation Method 1
parasitic capacitance coupling between adjacent memory cell floating gates becomes a problem
Data Source
AI summary
The present disclosure includes methods, devices, modules, and systems for operating non-volatile multilevel memory cells. One method embodiment includes assigning, to a first cell coupled to a row select line, a first number of program states to which the first cell can be programmed. The method includes assigning, to a second cell coupled to the row select line, a second number of program states to which the second cell can be programmed, wherein the second number of program states is greater than the first number of program states. The method includes programming the first cell to one of the first number of program states prior to programming the second cell to one of the second number of program states.