Memory-Centered Communication in Coarse-Grained Reconfigurable Arrays
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Solution Overview
Problem
The limited bandwidth and latency of the system bus in coarse-grained reconfigurable arrays (CGRAs) cause a bottleneck phenomenon when a processor transfers data to/from a frame buffer, leading to significant performance reduction and increased communication overheads, especially in applications with cyclic data dependency.
Innovation Solution
A memory-centralized communication apparatus is introduced, utilizing a central memory with single-port memory units and a cross-bar switch for direct communication between the processor, processing elements, and network/bus interface, eliminating the need for a multi-port memory and reducing reliance on the system bus.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a processor transfers data to/from a frame buffer through the system bus in a CGRA, then data communication between processor and memory is achieved, but bandwidth limitation and latency cause bottleneck phenomenon and performance reduction
Solution Approach 1:
The system is segmented into multiple independent communication paths: the system bus for processor-main memory communication, and separate direct memory access paths from processing elements to frame buffer. This segmentation allows parallel data transfer operations without mutual interference, eliminating the bottleneck caused by single-bus contention.
Solution Approach 2:
The frame buffer acts as an intermediary component between the processing elements and the main memory system. Processing elements can directly read/write to the frame buffer without involving the processor or system bus, enabling independent data staging operations that eliminate bus contention and reduce latency.
2Productivity
If a multi-port memory is used to enable direct communication between processor and PE array, then communication efficiency is improved, but area cost increases
Solution Approach 1:
Instead of using a single multi-port memory structure, the system segments memory resources into separate frame buffer and main memory components. Each component can be independently accessed, providing efficient communication paths without requiring complex multi-port memory architecture, thus reducing area cost while maintaining communication efficiency.
3Device complexity
If the system bus is used for all data transfers, then system simplicity is maintained, but communication overheads increase due to bus contention
Solution Approach 1:
The communication infrastructure is segmented into multiple independent channels: system bus for processor control and main memory access, and dedicated direct memory access paths for processing elements to frame buffer. This segmentation eliminates bus contention for data transfers, reducing communication overheads while adding minimal complexity through standardized interface connections.
Data Source
AI summary
The present invention relates to a coarse-grained reconfigurable array, comprising: at least one processor; a processing element array including a plurality of processing elements, and a configuration cache where commands being executed by the processing elements are saved; and a plurality of memory units forming a one-to-one mapping with the processor and the processing element array. The coarse-grained reconfigurable array further comprises a central memory performing data communications between the processor and the processing element array by switching the one-to-one mapping such that when the processor transfers data from/to a main memory to/from a frame buffer, a significant bottleneck phenomenon that may occur due to the limited bandwidth and latency of a system bus can be improved.