3D Memory Channel Pattern Layout for Etching Loss Reliability
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Solution Overview
Problem
Existing three-dimensional semiconductor memory devices face challenges in maintaining reliability due to the loss of channel pattern thickness during manufacturing processes, which affects operational performance.
Innovation Solution
The semiconductor memory device incorporates a stack structure with elliptical openings and channel patterns that have a thicker central portion and decreasing thickness towards the ends, ensuring the channel patterns are securely formed and maintaining structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional channel patterns with uniform thickness are used, then manufacturing simplicity is maintained, but thickness loss and resistance differences occur affecting reliability
Solution Approach 1:
The channel pattern is designed with non-uniform thickness distribution, where the central portion has greater thickness than the bent portions. This local variation in thickness compensates for etching loss and resistance differences, ensuring consistent electrical performance and reliability across different regions of the channel pattern.
Solution Approach 2:
The channel pattern transitions from a symmetric uniform thickness design to an asymmetric design where the central portion overlaps the major axis of the elliptical opening and has greater thickness. This asymmetric thickness distribution addresses the etching loss and resistance issues that occur in conventional symmetric designs.
2Manufacturing precision
If etching processes are applied to form channel patterns, then opening shapes are defined, but thickness loss occurs reducing channel current
Solution Approach 1:
The channel layer is formed with a predetermined non-uniform thickness profile before the etching process. The central portion is intentionally made thicker to compensate for the thickness loss that will occur during subsequent etching operations. This preliminary thickness compensation ensures that after etching, the channel pattern maintains adequate thickness and current carrying capacity.
3Reliability
If channel patterns are separated into multiple regions, then resistance differences are reduced, but manufacturing complexity increases
Solution Approach 1:
The channel layer is formed with spatially varying thickness properties, where the central portion has greater thickness than the bent portions. This local quality variation naturally creates distinct functional regions with different resistance characteristics, eliminating the need for complex multi-step separation processes while achieving resistance uniformity.
Data Source
AI summary
The present disclosure includes a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a stack including a plurality of conductive layers stacked to be spaced apart in a first direction, an opening in the stack extending in the first direction and having an elliptical shape in a plan view, and a first channel pattern and a second channel pattern spaced apart from each other in a second direction toward which a major axis of the elliptical shape faces in the opening, the first channel pattern and the second channel pattern extending in the first direction. Each of the first channel pattern and the second channel pattern includes a central portion overlapping with the major axis of the elliptical shape and bent portions extending away from the central portion.