3D Stacked Memory Charge Storage Segmentation
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Solution Overview
Problem
Three-dimensional stacked layer type semiconductor memory devices face challenges in improving writing/erasing characteristics and cycling resistance due to electron diffusion between adjacent memory cells, particularly when using silicon-rich SiN as a charge storage layer, leading to data loss.
Innovation Solution
The implementation of independent charge storage layers for each memory cell, achieved by physically separating them using insulating layers or cavities, allows for improved writing/erasing characteristics and cycling resistance, applicable to both SONOS and floating gate type memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon-rich SiN is used as a charge storage layer to improve writing/erasing characteristics and cycling resistance, then memory cell characteristics are improved, but electron diffusion occurs between adjacent memory cells causing data loss
Solution Approach 1:
The charge storage layer is divided into independent segments for each memory cell using insulating layers or cavities as separators. This segmentation prevents electron diffusion between adjacent memory cells while maintaining the beneficial characteristics of silicon-rich SiN within each isolated charge storage layer.
Solution Approach 2:
Insulating layers or cavities are introduced as intermediary structures between adjacent charge storage layers. These intermediaries act as barriers that block electron diffusion while allowing each charge storage layer to independently perform its charge storage function with improved writing/erasing characteristics.
2Reliability
If independent charge storage layers are implemented by adding insulating layers or cavities, then electron diffusion is prevented, but manufacturing process complexity increases
Solution Approach 1:
The insulating layers used to separate charge storage layers are integrated with the existing tunnel insulating layer structure. By merging the separation function with existing insulating layers, the design avoids adding completely new process steps while achieving electron diffusion prevention.
Solution Approach 2:
The insulating layers serve multiple functions: they act as tunnel insulating layers for charge injection and simultaneously serve as separation barriers between adjacent charge storage layers. This multi-functionality reduces the need for additional dedicated separation structures and simplifies the overall manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances the reliability of three-dimensional stacked layer type semiconductor memory by preventing electron diffusion between cells, thereby improving data retention and memory performance without significantly increasing the complexity of manufacturing processes.
Implementation Method 1
The implementation of independent charge storage layers for each memory cell, achieved by physically separating them using insulating layers or cavities
Data Source
AI summary
According to one embodiment, a nonvolatile semiconductor memory device includes first to n-th semiconductor layers which are stacked in a first direction perpendicular to a surface of a semiconductor substrate and which extend in a second direction parallel to the surface of the semiconductor substrate, an electrode which extends in the first direction along side surfaces of the first to n-th semiconductor layers, the side surfaces of the first to n-th semiconductor layers exposing in a third direction perpendicular to the first and second directions, and first to n-th charge storage layers located between the first to n-th semiconductor layers and the electrode respectively. The first to n-th charge storage layers are separated from each other in areas between the first to n-th semiconductor layers.