Nonvolatile Memory Unit Cell Charge Trap Segmentation

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Solution Overview

Problem

Nonvolatile memory devices face challenges in maintaining data stability due to interference effects and coupling capacitances between memory cells, particularly in densely packed flash memory devices with stacked gate structures, which can lead to unstable threshold voltages.

Innovation Solution

The design incorporates a unit cell with a substrate having active regions and charge trap patterns, junction regions, and control gate layers, where charge storage transistors share junction regions and are connected to word and bit lines, allowing for efficient charge trapping and programming operations, and includes a method of fabricating these structures with specific layer stacking and etching processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If memory cells are densely packed to increase integration density, then storage capacity is improved, but interference effects and coupling capacitances between cells increase causing threshold voltage instability

Engineering Contradiction:

Improveintegration densityVSAvoidthreshold voltage stability

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The memory cell is divided into separate floating gate and control gate structures, with charge trap patterns positioned between junction regions. This segmentation isolates charge storage functions from control functions, reducing interference between adjacent cells while maintaining high integration density through the stacked gate configuration.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Charge trap patterns are introduced as intermediary structures between the floating gate and control gate, and between adjacent junction regions. These intermediate charge trap patterns act as buffers that reduce direct coupling capacitance between neighboring memory cells, thereby stabilizing threshold voltages while allowing dense cell packing.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Adaptability or versatility

If additional equipment such as UV irradiator is added to erase data, then erasure capability is improved, but device complexity and convenience are worsened

Engineering Contradiction:

Improveerasure capabilityVSAvoidequipment requirement

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent replaces physical/chemical erasure mechanisms (UV irradiation required by traditional floating gate devices) with electrical field-based erasure through the control gate. The stacked gate structure enables electrical control of charge trapping and release, eliminating the need for UV irradiators and other external equipment, thereby simplifying the device while maintaining full erasure capability.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

3Area of stationary object

If charge trap patterns are positioned close to each other to reduce cell size, then area is reduced, but interference effects increase causing threshold voltage instability

Engineering Contradiction:

Improvecell areaVSAvoidthreshold voltage stability

Core Design Contradiction:

Area of stationary objectVSReliability

Solution Approach 1:

The patent transitions from planar charge trap arrangement to a vertical stacked gate structure. Charge trap patterns are positioned in the vertical dimension between the floating gate and control gate, rather than only in the lateral plane. This dimensional change allows reduced lateral cell area while maintaining adequate spacing between charge trap patterns to minimize interference effects and stabilize threshold voltages.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enhances data storage efficiency and stability by reducing interference effects, allowing for higher integration densities and improved programming and erasure operations in nonvolatile memory devices.

Implementation Method 1

a first tunneling layer, a first charge trap layer, a first insulation layer and a first control gate layer which are sequentially stacked

Methodology Applied

Scientific EffectTunneling:

Data Source

PatentUS9318569B2Unit cells of nonvolatile memory devices, cell arrays of nonvolatile memory devices, and methods of fabricating the same

Publication Date: 2016.04.19 SK HYNIX INC

AI summary

Unit cells including a substrate having an active region, a first charge trap pattern disposed on the substrate to intersect the active region, a second charge trap pattern disposed on the substrate to intersect the active region and spaced apart from the first charge trap pattern, a first junction region disposed in the active region between the first and second charge trap patterns, a second junction region disposed in the active region adjacent to one side of the first charge trap pattern opposite to the second charge trap pattern, and a third junction region disposed in the active region adjacent to one side of the second charge trap pattern opposite to the first charge trap pattern.