High Speed Memory Chip Module With TSV Metal Fence
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Solution Overview
Problem
Existing memory chip modules face challenges with high power consumption, poor heat dissipation, and noise interference due to differences in semiconductor process generations between memory and logic units, leading to manufacturing difficulties and inefficiencies.
Innovation Solution
A high-speed memory chip module design that integrates memory cell array groups with logic units via wider transmission buses, utilizing through-silicon vias (TSVs) to form a metal fence for enhanced electromagnetic interference shielding, heat dissipation, and noise isolation, while optimizing data transmission and power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If memory and logic units are integrated with different semiconductor process generations, then data transmission speed is improved, but power consumption increases and heat dissipation deteriorates
Solution Approach 1:
The patent applies parameter changes by adjusting the MOSFET gate length in the memory cell array to match the logic unit's process generation. Specifically, the memory cell array uses a second MOSFET gate length that is shorter than the first MOSFET gate length in the logic unit, optimizing the memory for higher speed while the logic unit maintains its advanced process characteristics, thereby resolving the power-speed tradeoff
Solution Approach 2:
The patent implements local quality by allowing different MOSFET process generations in different regions of the chip. The logic unit uses a first MOSFET process with gate length L1, while the memory cell array uses a second MOSFET process with gate length L2, where L2 < L1. This regional differentiation enables each component to operate at its optimal process node, improving overall system performance without excessive power consumption
2Productivity
If memory and logic units are integrated with different semiconductor process generations, then data transmission efficiency is improved, but heat dissipation capability deteriorates
Solution Approach 1:
The patent changes the MOSFET gate length parameter to optimize both speed and heat dissipation. The memory cell array uses a shorter second MOSFET gate length for high-speed operation, while the logic unit maintains a longer first MOSFET gate length that generates less heat during computation, achieving a balance between data transmission efficiency and thermal management
3Manufacturing precision
If memory and logic units are integrated with different semiconductor process generations, then manufacturing precision is improved, but noise interference increases
Solution Approach 1:
The patent applies local quality by creating distinct process regions with different MOSFET characteristics. The logic unit is fabricated with a first MOSFET process (gate length L1) optimized for low-noise computation, while the memory cell array uses a second MOSFET process (gate length L2) optimized for high-speed data storage and transmission. This spatial separation of process generations reduces cross-talk and noise interference between components
Solution Approach 2:
The patent introduces an intermediary approach by carefully designing the interface between the logic unit and memory cell array, using controlled signal routing and buffering to minimize noise coupling between the differently-processed components, thereby maintaining manufacturing precision while reducing noise interference
Data Source
AI summary
A high speed memory chip module includes a type of memory cell array group and a logic unit. The type memory cell array group includes multiple memory cell array integrated circuits (ICs), and each of the memory cell array ICs has a data bus and at least one memory cell array, and corresponds to first metal-oxide-semiconductor field-effect transistor (MOSFET) gate length corresponding to a first MOSFET process. The logic unit accesses the type of memory cell array group through a first transmission bus, where bus width of the first transmission bus is wider than bus width of the data bus of each of the memory cell array ICs. Corresponding to a second MOSFET process, the logic unit has a second MOSFET gate length which is shorter than the first MOSFET gate length.