Memory Chip Interface Using Multi-Level Signaling on a Shared Channel
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Solution Overview
Problem
Existing memory systems face challenges in enhancing performance and interface speed due to limitations in data transmission methods, particularly in semiconductor memory devices used in data storage devices like SSDs, which require improved signaling schemes to match the increasing operational speeds of host devices.
Innovation Solution
Implementing a multi-level signaling scheme, such as pulse amplitude modulation (PAM), where a data signal with multiple voltage levels represents multiple bits, allowing simultaneous data transmission and operation across multiple memory chips connected through a single channel, thereby improving data transmission rate without increasing frequency or power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a binary-symbol signal with two signal levels is used for data transmission, then the signaling scheme is simple and reliable, but the data transmission rate is limited and cannot meet the increasing interface speed requirements
Solution Approach 1:
The patent applies parameter changes by transitioning from a binary-symbol signal with two signal levels to a multi-level symbol signal with three or more signal levels. This changes the fundamental parameter of signal levels from 2 to 3 or more, enabling each symbol to represent multiple bits of data (e.g., 2 bits per symbol with 4 levels, or 3 bits per symbol with 8 levels). This directly increases the data transmission rate without proportionally increasing the symbol rate, thereby improving interface speed while maintaining reasonable signaling complexity
Solution Approach 2:
The patent introduces an additional dimension to data transmission by using multiple signal levels beyond the traditional binary approach. Instead of only varying the presence or absence of a signal (one dimension), the system varies the amplitude or voltage level across multiple discrete levels (adding another dimension). This dimensional expansion allows more information to be encoded per symbol period, effectively increasing bandwidth utilization and data rate without requiring additional physical channels
2Speed
If the interface speed between memory controller and semiconductor memory device is increased to match host device operating speed, then the data access speed improves, but the existing signaling schemes become insufficient and require complex modifications
Solution Approach 1:
The patent applies dynamics by implementing a configurable multi-level signaling scheme that can adapt to different operating conditions and requirements. The system dynamically selects among multiple signal levels (e.g., PAM2, PAM4, PAM8) based on the desired data rate, channel conditions, and performance requirements. This dynamic adaptability allows the interface to scale from 2 bits per symbol to 3 bits per symbol or more, providing flexibility to match varying host device operating speeds without requiring complete redesign of the signaling infrastructure
Solution Approach 2:
The patent implements universality by designing a multi-level signaling framework that can serve multiple functions and configurations within a single system. The same physical channel and hardware infrastructure can operate in different modes (binary, ternary, quaternary, or higher-order signaling) depending on the application requirements. This multi-functional capability allows the interface to accommodate various data rates and protocol requirements, making the signaling scheme versatile enough to handle both traditional and next-generation memory interface demands
3Productivity
If multiple memory chips are connected through a single channel, then the bandwidth is optimized and the symbol rate is reduced, but the data transmission method becomes more complex
Solution Approach 1:
The patent applies merging by combining multiple memory chip communications into a single shared channel that uses multi-level signaling. Instead of dedicating separate channels to each memory chip (which would require multiple independent signaling paths), the system merges the data streams and uses a unified multi-level symbol signal to carry data for multiple chips simultaneously. This consolidation increases bandwidth efficiency by better utilizing the available channel capacity while reducing the overall symbol rate required for the same effective data throughput
Solution Approach 2:
The patent applies parameter changes by modifying the signal level parameter from binary (2 levels) to multi-level (3 or more levels) to accommodate multiple memory chips on a single channel. This parameter change increases the information density per symbol, allowing the single channel to efficiently service multiple chips. The increased symbol rate capacity compensates for the need to multiplex multiple chip communications, ultimately achieving better bandwidth efficiency despite the more complex transmission method
Data Source
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AI summary
A memory system includes a memory controller and M memory chips. The memory controller generates a first data signal having one of 2M voltage levels different from each other, where M is a natural number greater than or equal to two, and outputs the first data signal through a first channel. The first data signal represents first data including M bits. The M memory chips are commonly connected to the memory controller through the first channel. When the M memory chips have an enabled state, the M memory chips simultaneously receives the first data signal transmitted through the first channel from the memory controller, and simultaneously obtains the M bits included in the first data based on the first data signal. Each of the M memory chips obtains a respective one of the M bits, and operates based on the respective one of the M bits.