Semiconductor Memory Chip Pad Arrangement for Signal Integrity

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Solution Overview

Problem

Existing semiconductor memory chips face challenges in efficiently connecting pads with different data bit configurations, leading to increased signal line lengths and complexity in printed circuit board (PCB) wiring configurations, which affects signal integrity and ease of fabrication.

Innovation Solution

The semiconductor memory chip design includes specific pad arrangements such as upper and lower data pads, strobe signal pads, and mask signal pads, with inverted termination and data mask signal pads connected internally to improve signal integrity and reduce signal line lengths between pads and balls, allowing for convenient PCB wiring configurations across different data bit configurations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If pads are arranged to support multiple data bit configurations, then adaptability is improved, but device complexity increases

Engineering Contradiction:

Improveadaptability to different data bit configurationsVSAvoidpad arrangement complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The semiconductor memory chip employs a universal pad arrangement where the same physical pads can serve multiple data bit configurations (e.g., 16-bit, 8-bit, 4-bit modes). The chip includes upper data pads, lower data pads, and additional pads that can be selectively activated depending on the required data width, allowing a single chip design to support various package configurations without requiring different pad layouts.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The pad array is segmented into functional groups including upper data pads, lower data pads, additional pads, and termination pads. This segmentation allows selective activation of different pad groups based on the required data bit configuration, enabling the same physical structure to support multiple operational modes while maintaining organized signal routing.

Inventive Principle:

Principle #1Segmentation

2Adaptability or versatility

If signal lines are extended to connect pads with different configurations, then signal line length increases, but signal integrity deteriorates

Engineering Contradiction:

Improvecompatibility across package configurationsVSAvoidsignal integrity

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The additional pads act as intermediaries between the upper and lower data pads, providing direct connection paths that eliminate the need for long signal lines traversing through the PCB. These intermediate pads enable shorter, more direct signal routing while maintaining compatibility across different package configurations, thereby preserving signal integrity.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The pad arrangement utilizes a multi-dimensional layout with upper, lower, and additional pad regions arranged in different spatial zones. This dimensional arrangement allows signal lines to connect pads more directly by utilizing vertical and horizontal spacing efficiently, reducing signal line length and improving signal integrity while supporting multiple data bit configurations.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Adaptability or versatility

If PCB wiring is configured for different data bit modes, then manufacturing complexity increases, but ease of manufacture decreases

Engineering Contradiction:

Improvesupport for multiple package typesVSAvoidPCB wiring configuration ease

Core Design Contradiction:

Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The semiconductor memory chip is pre-configured with a comprehensive pad arrangement that anticipates multiple data bit configurations. The upper, lower, and additional pads are positioned and internally connected in advance, allowing the PCB to simply follow the chip's predetermined pad layout regardless of the required data width. This preliminary configuration eliminates the need for complex PCB wiring variations across different package types.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

Instead of configuring PCB wiring differently for each data bit mode, the approach is inverted: the chip's pad arrangement is designed to accommodate all configurations, and the PCB uses a standardized wiring pattern that connects to the chip's pads. This inversion simplifies manufacturing by making the PCB design independent of the specific data bit configuration required.

Inventive Principle:

Principle #13The other way round (Inversion)

Data Source

PatentUS10679956B2Semiconductor memory chip, semiconductor memory package, and electronic system using the same

Publication Date: 2020.06.09 SAMSUNG ELECTRONICS CO LTD

AI summary

A semiconductor memory chip includes an upper data pad region, a lower data pad region, and an additional pad region. Upper data pads, upper data strobe signal pair pads, and an upper data mask signal pad are arranged in the upper data pad region. Lower data pads, lower data strobe signal pair pads, and a lower data mask signal pad are arranged in the lower data pad region adjacent to and below the upper data pad region. An inverted termination data strobe signal pad used for a second semiconductor memory package and internally connected to the upper data mask signal pad, which is used for a first semiconductor memory package, is arranged in the additional pad region adjacent to and above the upper data pad region.