Memory Chip Activation Signal Generator for SSD Capacity
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Solution Overview
Problem
The existing solid state disk (SSD) storage devices are limited in memory capacity due to the number of chip enable (CE) signals supported by the controller, requiring additional hardware and production process modifications to increase memory chips.
Innovation Solution
A storage device with a memory chip activation signal generator that combines existing CE signals to generate additional memory chip activation signals, allowing for increased memory capacity without additional CE signals, using a reconfigurable semiconductor chip and logic circuits to control and enable multiple memory chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory chips is increased to enhance storage capacity, then the memory capacity is improved, but the number of chip enable signals required increases, leading to additional hardware modifications
Solution Approach 1:
The patent segments the memory chips into multiple ranks (e.g., Rank 0, Rank 1, Rank 2) and uses a combination of chip enable signals and rank select signals to control access to different ranks. This segmentation allows the system to manage multiple memory chips using a smaller number of control signals by hierarchically organizing them.
Solution Approach 2:
The patent makes existing chip enable signals multi-functional by using them both as chip enable signals and as rank select signals. For example, CE0 can serve as both a chip enable signal for specific chips and as a rank select signal to identify a particular rank, thereby reducing the total number of signals needed.
2Quantity of substance
If additional chip enable signals are added to control more memory chips, then the memory capacity is increased, but the hardware modification requirements increase
Solution Approach 1:
The patent introduces a dynamic control mechanism where the controller can flexibly select which chip enable signal to activate based on the current operation. The rank select signals dynamically determine which rank of memory chips is accessible, allowing the same hardware to adapt to different memory chip configurations without physical modification.
Solution Approach 2:
The patent introduces rank select signals as intermediary control signals between the controller and the memory chips. These rank select signals work in conjunction with chip enable signals to mediate the control flow, allowing the controller to indirectly manage multiple memory chips through a hierarchical control structure rather than direct one-to-one control.
3Quantity of substance
If the controller supports more chip enable signals to increase memory capacity, then the storage capability is improved, but the controller complexity increases
Solution Approach 1:
The patent adds a new dimension to the control signal structure by introducing rank select signals that operate independently from chip enable signals. This dimensional separation allows the controller to manage memory chips in a hierarchical manner, where rank selection and chip enablement are separate control dimensions, thereby reducing the complexity of individual signal handling.
Solution Approach 2:
The patent implements preliminary rank selection before chip enablement. The controller first selects the desired rank using rank select signals, and then activates the appropriate chip enable signal. This preliminary action of rank selection simplifies the controller's operation by establishing the target rank before activating specific chips within that rank.
Data Source
AI summary
A device to selectively activate memory chips includes a memory unit including n memory chips activated in response to n memory chip activation signals (n is a natural number), a controller to generate m control signals (m is a natural number), and a memory chip activation signal generator to combine m chip enable (CE) signals to generate the n memory chip activation signals.