Memory Interface Chip Timing Alignment for Data-Clock Skew
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Solution Overview
Problem
Existing memory packages face issues with signal skew between data and clock signals, leading to reduced reliability and operational problems, particularly when interface chips are present, which complicates training operations and alignment.
Innovation Solution
Implementing a delay locked loop circuit and vernier-type delay circuit to adjust the phase difference between data and clock signals, allowing for precise alignment and removal of skew without additional training time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If an interface chip is connected between the host and memory chip to improve communication speed, then data exchange efficiency is improved, but signal skew between data and clock signals occurs leading to reduced reliability
Solution Approach 1:
The patent introduces a delay circuit as an intermediary component between the clock signal source and the memory interface. This delay circuit receives the clock signal and outputs a delayed clock signal, acting as a mediator to adjust the timing relationship between clock and data signals. The delay circuit includes delay elements that can be controlled to provide precise timing adjustment, resolving the signal skew issue while maintaining the high-speed communication capability provided by the interface chip.
Solution Approach 2:
The patent employs parameter changes by adjusting the delay amount of the clock signal through a controllable delay circuit. The delay circuit can vary the delay parameter based on training results or operational conditions, allowing dynamic optimization of the timing relationship between clock and data signals. This parameter adjustment mechanism enables the system to compensate for signal skew without sacrificing communication speed.
2Measurement precision
If delay circuits are added to remove signal skew, then signal alignment accuracy is improved, but device complexity increases
Solution Approach 1:
The delay circuit is segmented into multiple independent delay elements that can be individually controlled. Each delay element processes a portion of the clock signal, and their combined effect provides the total required delay. This segmentation allows for finer granularity in delay adjustment and simplifies the control logic, as each segment can be independently optimized and controlled, reducing overall circuit complexity while maintaining high alignment accuracy.
Solution Approach 2:
The delay circuit is designed with dynamic control capabilities, allowing the delay amount to be adjusted based on operational conditions. The circuit can switch between different delay states or continuously vary the delay parameter, enabling adaptive optimization of signal alignment. This dynamic behavior reduces the need for multiple fixed delay circuits, thereby simplifying the overall device complexity while maintaining precise signal alignment capability.
3Reliability
If additional training operations are performed to align signals, then signal synchronization is improved, but operation time increases
Solution Approach 1:
The delay circuit is configured to apply a preliminary delay to the clock signal before it reaches the memory interface, based on pre-characterized timing requirements. This preliminary action anticipates the needed alignment adjustment, reducing or eliminating the need for extensive training operations. The delay amount can be predetermined based on device characteristics, allowing the system to achieve proper synchronization with minimal training time.
Solution Approach 2:
The delay circuit is designed to automatically adjust its delay parameter based on built-in feedback mechanisms or pre-stored calibration data. The circuit can self-calibrate during initialization or adaptively adjust during operation without requiring extensive external training sequences. This self-service capability reduces the training time burden while maintaining reliable signal synchronization.
Data Source
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AI summary
A memory package (20) includes a plurality of memory chips (22), and an interface chip (21) relaying communications between a controller (10) and the plurality of memory chips (22) and receiving a plurality of signals from the plurality of memory chips (22). The interface chip (21) includes receivers outputting a data signal and a raw clock signal based on the plurality of signals, a delay circuit outputting a delay clock signal by applying an offset delay corresponding to 1/2 of one unit interval of the data signal and an additional delay to the raw clock signal, and a sampler sampling the data signal in synchronization with a clock signal. The delay circuit outputs the clock signal generated by removing the offset delay from the delay clock signal when the delay clock signal and the data signal have a phase difference corresponding to one unit interval of the data signal.