Memory Circuit Analog Bypass for Concurrent Read Write
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Solution Overview
Problem
Classical and quantum computing systems face challenges with memory circuits that lack adequate capacity and speed relative to logic circuits, particularly in avoiding timing errors during concurrent write and read operations in memory arrays.
Innovation Solution
A memory circuit with an analog bypass portion that includes a write-through detection system to activate an analog bypass portion when a write address matches a read address, allowing data to be read concurrently with writing by deactivating the read address decoder and using the analog bypass portion to read data from bit-write signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional memory array is used for concurrent write and read operations, then data storage capacity is maintained, but timing errors occur when read address matches write address
Solution Approach 1:
The memory array is segmented into two distinct portions: a digital portion for conventional memory operations and an analog bypass portion for write-through operations. This segmentation allows the system to handle concurrent write and read operations by routing them through different paths, eliminating timing errors that would occur in a unified conventional memory array.
Solution Approach 2:
The analog bypass portion acts as an intermediary structure between the write and read operations. When a timing conflict is detected (read address matches write address), the system activates the analog bypass portion to handle the read operation, allowing the digital portion to complete the write operation without interference. This intermediary structure mediates the conflict between concurrent write and read operations.
2Reliability
If the read operation waits for write operation completion, then timing errors are avoided, but data access speed decreases
Solution Approach 1:
The system performs preliminary detection of address matching between read and write operations. When a match is detected, the analog bypass portion is pre-configured and activated before the write operation completes, allowing the read operation to proceed concurrently without waiting for write completion. This preliminary action prevents the need to slow down data access while maintaining timing error avoidance.
Solution Approach 2:
The system changes the operational parameters of the memory circuit by switching between digital and analog modes. During normal operations, the digital portion operates at standard speeds. When a timing conflict is detected, the system transitions to analog mode in the bypass portion, which operates with different timing parameters that allow concurrent read and write operations without timing errors, thereby maintaining high data access speed.
3Productivity
If an analog bypass portion is added to the memory array, then concurrent read and write operations are enabled, but device complexity increases
Solution Approach 1:
The analog bypass portion is designed to perform multiple functions: it serves as a read path during write-through operations, acts as a buffer during transitions, and can be integrated with the existing digital memory structure. This multi-functionality reduces the need for additional separate components, thereby limiting the increase in device complexity while enabling concurrent read and write operations.
Solution Approach 2:
The analog bypass portion is merged with the existing digital memory array structure, sharing common components such as bit lines, word lines, and control logic. This merging approach allows the system to add concurrent operation capability without duplicating entire memory structures, thereby limiting the increase in device complexity. The analog and digital portions work together as an integrated system rather than separate entities.
Data Source
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AI summary
One example includes a memory circuit. The circuit includes a memory array arranged as rows and columns of memory cells. An array portion stores a respective memory word in a given one of the rows in response to a word-write signal corresponding to a write address of the given one of the rows and in response to a plurality of bit-write signals associated with the plurality of columns, and reads a respective memory word from a given one of the rows in response to a word-read signal corresponding to a read address of the given one of the rows and in response to a plurality of bit-read signals associated with the plurality of columns. The circuit also includes a write-through detection system that activates an analog bypass portion to read the memory word from the analog bypass portion in response to the read address being equal to the write address.