Memory Circuit Topology With Secondary Pre-Charge for Stable Bit-Line Reads
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Solution Overview
Problem
Memory cell read operations are affected by changes in power supply voltage, leading to inaccurate results due to issues like floating bit line voltages and performance penalties during power saving modes.
Innovation Solution
Incorporating a secondary pre-charge transistor coupled to each bit line, with a column select transistor between the secondary pre-charge and power supply node, to maintain bit line voltage within a specified range using transistors of opposite polarity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If power supply voltage is reduced for power saving, then energy consumption decreases, but bit line voltage becomes unstable and read accuracy deteriorates
Solution Approach 1:
A secondary pre-charge transistor is introduced as an intermediary component between the primary pre-charge transistor and the bit line. This secondary transistor acts as a mediator that maintains stable bit line voltage during power saving modes by providing an additional pre-charge path, thereby resolving the conflict between reduced power consumption and maintained read accuracy.
Solution Approach 2:
The secondary pre-charge transistor performs preliminary pre-charging of the bit line before the main read operation occurs. By pre-establishing a stable voltage baseline through the secondary transistor, the system prepares the bit line in advance to withstand power supply fluctuations, ensuring accurate read operations even when main power is reduced.
2Device complexity
If primary pre-charge transistor is used alone, then device complexity is low, but bit line voltage floats during power saving modes
Solution Approach 1:
The secondary pre-charge transistor serves as a stabilizing intermediary that prevents bit line voltage from floating. By introducing this additional transistor with opposite polarity, the system gains a controlled pre-charge path that anchors the bit line voltage to a stable reference, eliminating the floating voltage issue while maintaining relatively simple circuit architecture.
3Stability of the object's composition
If secondary pre-charge transistor is added, then bit line voltage stability improves, but device complexity increases
Solution Approach 1:
The pre-charge function is segmented into two distinct transistors: a primary pre-charge transistor for normal operation and a secondary pre-charge transistor for power saving modes. This segmentation allows each transistor to be optimized for its specific function and enables the system to maintain stable bit line voltage across different power modes without requiring a completely redesigned circuit.
Solution Approach 2:
The secondary pre-charge transistor is strategically positioned and configured with opposite polarity to address the specific local issue of bit line voltage instability during power saving modes. This localized solution targets the precise problem area (bit line pre-charging) without unnecessarily complicating other parts of the memory circuit.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Prevents bit line voltage floating and improves read operation performance by ensuring consistent discharge times, independent of power supply fluctuations.
Implementation Method 1
Incorporating a secondary pre-charge transistor coupled to each bit line, with a column select transistor between the secondary pre-charge and power supply node, to maintain bit line voltage within a specified range using transistors of opposite polarity
Implementation Method 2
improves read operation performance by ensuring consistent discharge times, independent of power supply fluctuations
Data Source
AI summary
Embodiments herein relate to a memory device in which a secondary pre-charge transistor is coupled to each bit line in an array of memory cells. A column select transistor such as an nMOS is between the secondary pre-charge transistor such as a pMOS and a power supply node. The secondary pre-charge transistor and the column select transistor have their control gates connected so that they are controlled by a common control signal. The secondary pre-charge transistor prevents floating of the bit line voltage in a read operation and maintains a voltage of the bit line in a specified range.