Memory Clock Gating Circuit for Command-Matched Cycle Control
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Solution Overview
Problem
Dynamic power consumption in memories, such as DRAM, is high due to continuous flipping of clock signals during operations that do not match the required command times, leading to unnecessary cycles.
Innovation Solution
A clock signal generation circuit and method that includes a command predecoding circuit, a command decoding circuit, and a counter circuit to generate a target clock signal that matches the operation time of each command, intercepting unnecessary clock cycles to reduce dynamic power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a uniform clock signal is used for all command operations, then the clock signal generation is simple, but dynamic power consumption increases due to unnecessary clock flipping during operations that do not match command times
Solution Approach 1:
The patent implements dynamic clock signal generation by using a counter circuit to track the number of clock cycles required for different command types. The clock signal is enabled only during the necessary cycles for each specific command (read, write, refresh), and disabled during unnecessary cycles, thereby dynamically adapting the clock signal to match the actual operational requirements and reducing dynamic power consumption.
Solution Approach 2:
The patent changes the operational parameters of the clock signal based on the command type. By using a counter circuit to determine the required number of clock cycles for each command (e.g., different cycle counts for read vs. write operations), the system adjusts the clock signal duration and frequency to match the specific operational needs, avoiding unnecessary clock transitions and reducing power consumption.
2Adaptability or versatility
If the clock signal cycle is extended to cover all possible command operations, then all commands can be supported, but unnecessary clock cycles are generated for specific commands, increasing dynamic loss
Solution Approach 1:
The system dynamically adjusts the clock signal duration based on the specific command being executed. The counter circuit is configured with different count values corresponding to different command types (read, write, refresh), and the clock signal is generated only for the necessary number of cycles for each command, thereby maintaining versatility while minimizing unnecessary clock cycles and dynamic loss.
Solution Approach 2:
The patent employs periodic clock signal generation where the clock is activated in specific periods corresponding to the duration of each command operation. The counter circuit controls the periodic activation, enabling the clock signal only during the required cycles for each command type and disabling it during unnecessary periods, thus reducing dynamic loss while supporting all command operations.
3Ease of operation
If the clock signal is continuously generated without interception, then timing for all commands is simplified, but unnecessary clock cycles cause continuous flipping and increase dynamic power consumption
Solution Approach 1:
The patent extracts and removes unnecessary clock cycles from the continuous clock signal through a clock interception mechanism. The counter circuit identifies the specific number of cycles needed for each command and intercepts (enables) the clock signal only during those necessary cycles, while disabling it during unnecessary cycles, thereby eliminating continuous flipping and reducing dynamic power consumption while maintaining ease of timing control.
Solution Approach 2:
The system dynamically controls the clock signal generation by using the counter circuit to determine the exact duration needed for each command. The clock signal is generated dynamically only when and for as long as needed, rather than continuously, allowing the system to maintain simple timing control logic while significantly reducing unnecessary clock transitions and power consumption.
Data Source
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AI summary
The present disclosure provides a clock signal generation circuit and method, and a memory, and relates to the field of semiconductor technologies. The circuit includes: a command predecoding circuit, configured to decode partial command bits in a command, to obtain a predecoded command signal; a command decoding circuit, configured to decode the command, to obtain an internal command signal; a counter circuit, configured to count a clock cycle based on an initial clock signal, to generate a first counting signal and a second counting signal; and a clock signal interception circuit, connected to the command predecoding circuit, the command decoding circuit, and the counter circuit, and configured to intercept the initial clock signal based on the predecoded command signal, the internal command signal, the first counting signal, and the second counting signal, to obtain a target clock signal. According to embodiments of the present disclosure, a dynamic loss of the memory can be reduced.