Memory Clock Synchronization for Hazard-Free Debug Timing
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Solution Overview
Problem
Existing memory testing techniques fail to properly manage internal clock timings during debug modes, leading to timing hazards that impact functionality and yield, rendering the debug feature inoperable.
Innovation Solution
A memory architecture that controls internal clock timings using an external clock synchronized operation, where the rising edge of the external clock triggers a self-time loop and the falling edge manages critical timings, ensuring proper synchronization and preventing timing hazards during test or debug operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory uses self-timed internal clock operation during functional mode, then the memory achieves efficient normal operation, but timing hazards occur during test/debug modes that render the debug feature inoperable
Solution Approach 1:
The system dynamically switches between two clocking modes: self-timed mode for functional operation and external clock mode for test/debug operations. The clock generation circuit responds to test mode signals to select the appropriate timing source, enabling the system to adapt its timing behavior based on operational context.
Solution Approach 2:
The patent changes the clock timing parameters by switching from internal self-timed generation to external clock synchronization during test modes. This parameter change allows precise control of clock edges (rising and falling) to match functional mode timing while enabling accurate measurement during debugging.
2Manufacturing precision
If the external clock is used to trigger internal clock generation, then the memory achieves synchronized operation, but timing hazards occur during test modes due to improper management of internal clock timings
Solution Approach 1:
The clock generation system is segmented into separate control paths: one for functional mode operation and another for test/debug mode operation. The test mode control logic separates the timing management for rising edges and falling edges, allowing independent optimization and measurement of each edge's timing behavior.
Solution Approach 2:
The patent introduces test mode control logic as an intermediary between the external clock input and the internal clock generation circuitry. This intermediary manages the timing signals during test modes, ensuring proper synchronization while preventing timing hazards that would otherwise occur during debugging operations.
3Productivity
If the rising edge of external clock triggers self-time loop, then the memory achieves efficient clock generation, but the falling edge timing cannot be properly utilized for measurement during test modes
Solution Approach 1:
The external clock signal serves multiple functions simultaneously: it triggers the self-time loop on its rising edge for efficient clock generation, and it provides a measurable reference on its falling edge for timing measurements during test modes. The system is designed to utilize both edges of the clock signal for different purposes.
Solution Approach 2:
The system implements feedback mechanisms that allow the falling edge of the external clock to be captured and measured while maintaining the self-timed operation initiated by the rising edge. This feedback enables accurate timing measurement during test modes without disrupting the efficient clock generation during functional modes.
Data Source
AI summary
A method and system are provided for controlling clock operation in a memory that applies a test mode to test functionality of the memory which controls timing in a self-time loop using an external clock that on a rising edge triggers a main clock and on a falling edge provides a reset timer return path to reset the main clock signal. In the reset timer return path, a rising edge of the external clock triggers start of a self-time loop, and the rising edge of the external clock also controls the reset timer return path to block generation of a reference bit line (RBL) signal. In the reset timer return path, a falling edge of the external clock generates the RBL signal to provide an external clock return signal to enable an end of cycle for the self-time loop.