Memory Clock Timing-Drift Calibration Using Oscillator Feedback
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Solution Overview
Problem
Integrated circuit devices, particularly memory devices, face significant timing drift due to temperature changes, leading to inaccuracies in clock distribution circuits, especially when transitioning between power states, which existing technologies fail to adequately address.
Innovation Solution
A system with a memory device incorporating an oscillator circuit to measure frequency changes, allowing for the derivation of timing drift, and a memory controller that triggers and processes these measurements to determine necessary calibration updates, thereby adjusting for timing drift.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the memory device transitions between power states to save power, then power consumption is reduced, but timing drift increases due to temperature changes
Solution Approach 1:
The system performs preliminary timing calibration before power state transitions and after transitions occur. A calibration command is issued to the memory device to measure timing parameters at different temperature conditions, and calibration data is stored for later application. This preliminary action prepares the system to compensate for timing drift that will occur during power state transitions.
Solution Approach 2:
The system implements feedback by measuring actual timing parameters using oscillator circuits and counters during calibration, comparing these measurements against reference values, and using the difference to adjust timing parameters. The calibration process continuously monitors timing drift and adjusts compensation values to maintain timing accuracy despite temperature variations from power state transitions.
2Measurement precision
If frequency measurement is performed continuously to track timing drift, then timing accuracy is maintained, but power consumption increases
Solution Approach 1:
Instead of continuous measurement, the system performs frequency measurements periodically at scheduled intervals. The memory controller issues calibration commands at predetermined times to measure timing parameters, processes the measurements, and updates calibration data only when necessary. This periodic approach maintains timing accuracy while significantly reducing power consumption compared to continuous monitoring.
3Reliability
If calibration is performed frequently to maintain timing accuracy, then timing drift is compensated, but productivity decreases
Solution Approach 1:
The system dynamically adjusts calibration frequency based on actual timing drift conditions rather than using a fixed schedule. The memory controller monitors timing parameters and performs calibration only when drift exceeds thresholds or when power state transitions occur. This dynamic approach maintains timing accuracy while minimizing interruptions to memory operations and maximizing productivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively calibrates timing drift, maintaining accuracy and reducing power consumption by dynamically determining calibration intervals based on measured frequency changes, thus mitigating the impact of temperature-induced timing variations.
Implementation Method 1
a relatively large rate of temperature change (often referred to as 'temperature-drift-rate,' in deg C./ms) due to self-heating when transitioning from a low-power state to an active state and/or self-cooling when transitioning from an active state to a low-power state. This large temperature-drift-rate can cause a significant timing drift over a short period of time, for example, because of the temperature sensitivity of clock distribution circuits (ps/deg C.) in a memory device.
Data Source
AI summary
The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit.