Quadrature-Corrected Memory Clock Circuit for Duty Error Control
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Solution Overview
Problem
Semiconductor memory devices face issues with clock skew and duty errors that affect data input/output speed and reliability, leading to potential malfunctions due to insufficient setup and hold margins.
Innovation Solution
A semiconductor memory device with a data clock buffer, edge delay controller, unit delay path circuits, and quadrature error correction circuit to adjust and correct clock skew and duty cycles, generating multiple phased clock signals for synchronized data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a synchronous memory device is used to input/output data in synchronization with a received system clock, then data transfer reliability is improved, but clock skew and duty error occur due to internal circuits
Solution Approach 1:
The patent applies preliminary action by detecting clock skew and duty cycle errors before they affect data transfer operations. The detection circuit measures the actual clock signal parameters in advance, and the correction circuit pre-adjusts the clock signals to compensate for expected deviations, ensuring that when data transfer occurs, the clock signals are already optimized for reliable operation.
Solution Approach 2:
The patent implements feedback by using a detection circuit that continuously monitors the clock signals generated by internal circuits. The detected information about clock skew and duty cycle errors is fed back to a correction circuit, which adjusts the clock signals in real-time. This closed-loop feedback mechanism ensures that clock signal precision is maintained despite variations in internal circuit performance.
2Speed
If the clock applied from the outside is used inside the memory device, then operation speed is improved, but time delay (clock skew) and duty error occur
Solution Approach 1:
The patent introduces an intermediary correction circuit between the externally applied clock and the internal circuits that require clock signals. This intermediary circuit detects the actual clock signal characteristics and generates corrected clock signals that serve as a mediator, eliminating the direct harmful effect of clock skew and duty error while maintaining the high-speed operation enabled by the external clock.
Solution Approach 2:
The patent replaces the direct mechanical/electrical connection between the external clock and internal circuits with an electronic correction system. Instead of relying on the physical clock distribution network to maintain precision, the system uses electronic detection and correction circuits to substitute for the inadequate direct connection, achieving both high speed and high precision.
3Device complexity
If clock skew and duty error are not corrected, then device complexity is reduced, but setup margin or hold margin for entire operation becomes insufficient
Solution Approach 1:
The patent applies partial action by implementing correction only for the specific parameters that affect operation margin (clock skew and duty cycle), rather than redesigning the entire clock distribution system. The correction circuit focuses on the critical aspects of clock signal quality, providing sufficient operation margin without the excessive complexity that would result from a complete system redesign.
Data Source
AI summary
A semiconductor memory device is provided. The semiconductor includes a data clock buffer that receives a data clock signal from a memory controller and outputs a pair of differential input signals, an edge delay controller that adjusts duty ratios of the pair of differential input signals based on a control code and outputs a pair of corrected clock signals, a first unit delay path circuit that generates four output clock signals having different phases based on the pair of corrected clock signals, a rising edge multiplexer that serially outputs data corresponding to a rising edge of each of the four output clock signals, a second unit delay path circuit that generates four duplicate clock signals having different phases based on the pair of corrected clock signals and a quadrature error correction circuit detector that detects a duty error based on the duplicate clock signals and outputs the control code.