Memory Clock Mode Configuration for Signal Integrity and Power
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Solution Overview
Problem
The existing flash memory systems face performance limitations due to signal integrity issues such as crosstalk, signal skew, and simultaneous switching noise, as well as power consumption challenges, especially when a large number of memory devices are connected in parallel, which restricts the system's ability to operate at high speeds and increases costs.
Innovation Solution
A serially connected memory system is introduced, where memory devices are connected in a ring topology, allowing for either parallel or serial clock signals, and a configurable memory device with a mode setter and clock switch circuit that adjusts its operation based on a reference voltage to optimize clock and data input/output operations, enabling high-speed and low-power modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory devices are connected in parallel to increase storage capacity, then the available storage capacity increases, but signal integrity deteriorates due to crosstalk, signal skew, and simultaneous switching noise
Solution Approach 1:
The patent divides the parallel-connected memory devices into groups, with each group having its own dedicated clock signal path. This segmentation reduces the number of devices sharing a single clock line, thereby reducing crosstalk and signal skew while still achieving high storage capacity through the grouped parallel architecture.
2Quantity of substance
If multiple memory devices are connected in parallel to increase storage capacity, then the available storage capacity increases, but power consumption increases due to frequent charging and discharging of signal tracks
Solution Approach 1:
The patent segments the memory devices into groups, each with dedicated clock signal paths. This reduces the total number of clock lines required compared to fully parallel connection, thereby reducing the power consumption associated with charging and discharging signal tracks while maintaining high storage capacity through grouped parallel architecture.
3Speed
If system clock frequency is increased to improve operation speed, then the operation speed increases, but power consumption increases
Solution Approach 1:
The patent implements dynamic clock gating that selectively enables or disables clock signals to different memory device groups based on operational requirements. This allows the system to achieve high operation speeds when needed while reducing power consumption during lower-demand operations by eliminating unnecessary clock signal switching.
4Quantity of substance
If the number of memory devices connected in parallel is increased, then the storage capacity increases, but the system becomes limited by drive capability and loading of signal tracks
Solution Approach 1:
The patent segments memory devices into multiple groups, each group connected through its own dedicated clock signal path. This segmentation distributes the loading across multiple signal tracks rather than overloading a single shared clock line, enabling the system to support more memory devices and achieve higher storage capacity without exceeding signal track drive capability limits.
Data Source
AI summary
A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.