Memory Clock Timing Control for Multi-Bank Sampling Accuracy
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Solution Overview
Problem
Memory devices face compatibility issues with various access modes, particularly in 16 bank access mode, due to insufficient timing adjustments in the internal clock signal, leading to errors in data sampling.
Innovation Solution
The memory device incorporates a timing control circuit that regulates the pulse width and delay time of the internal clock signal in response to access mode signals, ensuring that sampling signals accurately fall within data and interval periods, thereby improving compatibility with different access modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the internal clock signal uses fixed pulse width, then the circuit design is simple, but data sampling accuracy deteriorates in different access modes
Solution Approach 1:
The patent implements dynamic pulse width adjustment for the internal clock signal based on different access modes. The timing control circuit receives mode signals and dynamically adjusts the pulse width of the internal clock signal to match the timing requirements of different access modes (16 bank access, bank group access, etc.), thereby achieving accurate data sampling without requiring completely different circuit designs for each mode
Solution Approach 2:
The patent changes the temporal parameter (pulse width) of the internal clock signal according to different access modes. By adjusting the pulse width parameter dynamically based on mode signals, the system adapts to different timing requirements while maintaining a unified circuit architecture, resolving the contradiction between sampling accuracy and circuit complexity
2Adaptability or versatility
If the memory device supports multiple access modes, then the adaptability is improved, but the timing control accuracy deteriorates
Solution Approach 1:
The patent segments the timing control into different branches based on access modes. The timing control circuit includes separate processing paths for different modes (16 bank access mode, bank group access mode), with each path having optimized timing parameters. This segmentation allows each mode to have precise timing control while maintaining multi-mode support
Solution Approach 2:
The patent introduces mode signals as intermediaries between the access mode selection and the internal clock signal generation. These mode signals act as mediators that carry timing requirement information from the control logic to the timing control circuit, enabling accurate timing adjustment for different access modes without direct complex interconnections
3Reliability
If the sampling signal timing is not adjusted, then the circuit operation is simple, but data sampling errors occur in specific access modes
Solution Approach 1:
The patent performs preliminary timing adjustment of the internal clock signal based on the predicted access mode. The timing control circuit proactively adjusts the pulse width before data sampling occurs, ensuring that the clock signal is already optimized for the upcoming operation. This prevents sampling errors without requiring complex real-time correction mechanisms
Data Source
AI summary
A memory device includes: a memory cell array including M bank groups, each of which includes N banks; a peripheral circuit coupled to the memory cell array and configured to: regulate an internal clock signal in response to a first access mode signal and output a first clock signal; output a first data signal in response to the first clock signal and a first local data signal, wherein the first local data signal comprises a plurality of first data periods and a plurality of first interval periods alternating with the plurality of first data periods, and two adjacent ones of the first sampling signals fall respectively in the first data period and the first interval period adjacent to each other; and write the first data signal into a target bank of the (M*N) banks.