Memory Clock Tree Structure Using Dual Internal Clock Signals
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Solution Overview
Problem
Semiconductor memory devices face timing issues due to increased wire resistance, which causes longer delays and signal integrity problems in driving the internal clock to all memory banks, particularly affecting the clock to word line time.
Innovation Solution
Generating two internal clock signals, ICLK[0] and ICLK[1], where ICLK[1] is faster than ICLK[0], and using these signals to improve the rising and falling slope of the clock signal within local clock drivers, specifically through NAND and NOR gates, to reduce clock to word line delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single internal clock signal is used to drive all memory banks, then the device complexity is reduced, but the clock to word line delay increases due to wire resistance
Solution Approach 1:
The patent divides the single internal clock signal into multiple segmented clock signals (ICLK[0] and ICLK[1]) that are distributed to different memory banks. This segmentation allows each bank to receive a locally optimized clock signal, reducing the overall clock to word line delay across the memory device while maintaining manageable complexity through systematic distribution.
Solution Approach 2:
The patent implements local quality by providing different clock signal characteristics to different memory banks based on their specific needs. The first internal clock signal ICLK[0] is provided to first memory banks while the second internal clock signal ICLK[1] is provided to second memory banks, allowing each bank to have optimized clock timing characteristics for its local region.
2Reliability
If the clock signal is driven across long wire distances to all memory banks, then all banks can be clocked, but signal integrity deteriorates due to increased wire resistance
Solution Approach 1:
The patent segments the clock distribution network into multiple parallel paths, each serving specific memory banks. By dividing the long wire distance into shorter segmented paths with separate clock signals ICLK[0] and ICLK[1], the patent reduces wire resistance and maintains signal integrity in each segment while collectively covering all memory banks.
3Productivity
If the clock to word line time is reduced, then memory access speed improves, but the rising and falling edges of the clock signal become more critical
Solution Approach 1:
The patent applies local quality by providing different clock signal characteristics to different memory banks. The first internal clock signal ICLK[0] with specific timing characteristics is provided to first memory banks, while the second internal clock signal ICLK[1] is provided to second memory banks, allowing each bank to have optimized clock edge timing for high-speed operation.
Solution Approach 2:
The patent uses preliminary action by providing a second internal clock signal ICLK[1] that is faster than the first signal ICLK[0] to specific memory banks. This faster clock signal is used to pre-charge or pre-position data in anticipation of the main clock edge, effectively reducing the clock to word line time and improving memory access speed before the critical edge arrives.
Data Source
AI summary
Systems and methods are provided a memory circuit that provides multiple clock signals to a local clock driver. One of the clock signals may be faster than the other and, as a result, at least one transistor of the local clock driver may be turned on early to improve the delay of the rising edge, the falling edge, or both edges of the slower clock signal. The local clock driver may include a first transistor electrically connected to the NAND gate and a second transistor electrically connected to the NOR gate. As a result of the additional, faster clock signal, a reduction of the clock to word line time in the memory circuit can be achieved.