Semiconductor Memory Clock Generation for High-Speed Write Operations
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Solution Overview
Problem
Semiconductor memory devices for mobile electronic devices face challenges in reducing power consumption and maintaining a sufficient margin between data and data output strobe signals as operating frequencies increase, leading to potential write operation failures.
Innovation Solution
A semiconductor memory device is designed with a command decoder generating an auto-sync signal and an internal data clock generating circuit that adjusts the phase of a second clock relative to a first clock, allowing the data clock to operate at a higher frequency than the system clock, and includes a dual clock managing circuit to selectively activate different clock generators for write and read operations, ensuring efficient power use and data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the operating frequency of semiconductor memory devices is increased to support multi-tasking and higher speed operations, then productivity is improved, but the margin tDQSS between data and data output strobe signal becomes tighter causing write operation failures
Solution Approach 1:
The patent changes the clocking parameter from DQS-based to WCLK-based clocking method. The WCLK clocking method uses a system clock that is provided from the application processor and remains in a free running state, changing the fundamental parameter of how data transfer is synchronized. This resolves the contradiction by providing a more stable timing reference that maintains adequate margins even at high operating frequencies.
Solution Approach 2:
Instead of using the data output strobe signal (DQS) from the memory device to clock data transfers, the patent inverts the approach by using a system clock (WCLK) provided from the application processor. This inversion of the clocking source provides better control over timing margins and allows the data clock to remain stable during power-down modes, resolving the reliability issue at high frequencies.
2Ease of operation
If the DQS clocking method is used with data output strobe signal from the memory device, then ease of operation is maintained, but power consumption increases and timing margin becomes insufficient at high frequencies
Solution Approach 1:
The patent changes the clocking parameter from DQS-based to WCLK-based clocking method. The WCLK clocking method uses a system clock that is provided from the application processor and remains in a free running state, changing the fundamental parameter of how data transfer is synchronized. This resolves the contradiction by providing a more stable timing reference that maintains adequate margins even at high operating frequencies.
Solution Approach 2:
Instead of using the data output strobe signal (DQS) from the memory device to clock data transfers, the patent inverts the approach by using a system clock (WCLK) provided from the application processor. This inversion of the clocking source provides better control over timing margins and allows the data clock to remain stable during power-down modes, resolving the reliability issue at high frequencies.
Data Source
AI summary
A semiconductor memory device includes a command decoder configured to generate an auto-sync signal in response to a command for writing data at a memory cell or reading data from a memory cell, and an internal data clock generating circuit configured to phase synchronize a second clock, having a clock frequency higher than a clock frequency of a first clock, with the first clock in response to the auto-sync signal.