Memory Column Multi-Cell Switching for Adjacent Cell Repair
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Solution Overview
Problem
Conventional memory repair techniques are inefficient in handling multiple adjacent defective memory cells in a column, leading to reduced yield and increased die costs in integrated circuit fabrication.
Innovation Solution
Implementing multi-cell switching circuitry that couples or decouples multiple memory cells based on the identification of defective cells, allowing spare cells to replace adjacent defective cells, thereby enhancing the effective yield of integrated circuit fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional cell-specific memory repair techniques are used, then each defective cell can be individually addressed, but the circuit design becomes complex and yield decreases when multiple adjacent cells are defective
Solution Approach 1:
The patent merges multiple cell-specific repair operations into a single multi-cell switching operation. When multiple adjacent cells in a column are defective, the switching circuitry simultaneously redirects multiple signal lines to corresponding spare cells, rather than performing individual cell-by-cell repairs. This reduces circuit complexity while maintaining comprehensive repair capability.
Solution Approach 2:
The switching circuitry is designed to handle both single-cell and multi-cell repair scenarios with a unified architecture. The same switching mechanism can redirect one cell or multiple adjacent cells to spare cells, providing universal repair functionality that adapts to different defect patterns without requiring separate circuit designs.
2Reliability
If conventional memory repair techniques are used, then individual defective cells can be replaced, but effective yield decreases due to the inability to efficiently handle multiple adjacent defective cells
Solution Approach 1:
The patent performs preliminary identification of multiple adjacent defective cells during manufacturing testing, and pre-configures the switching circuitry to redirect all identified defective cells to appropriate spare cells in a single operation. This preliminary action prevents the need for iterative repairs and maximizes effective yield by efficiently utilizing available spare cells.
Solution Approach 2:
The memory device performs self-repair by automatically detecting defective cells and reconfiguring its internal switching circuitry to route signals through spare cells. This self-service capability eliminates the need for external repair intervention, improving fabrication productivity by allowing devices with multiple defective cells to be salvaged automatically.
Data Source
AI summary
Techniques and mechanisms for a memory device to support memory repair functionality for a column of a memory array. In an embodiment, the column comprises first memory cells and second memory cells, where switch circuitry is coupled between multiple signal lines and the column. Control circuitry transitions the switch circuitry to a state which corresponds to a defective one of the first cells. The state switchedly decouples the defective cell, and an adjoining one of the first cells, each from respective ones of the signal lines. During the state, two or more of the signal lines are able to communicate each to a different respective one of the second cells. In another embodiment, the switch circuitry is transitioned to the state based on an identifier of the defective cell, and independent of whether any other cell of the column has been identified as defective.