Memory Column Plane Layout for Single-Pass ECC and Metadata Access
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Solution Overview
Problem
Existing memory devices face limitations in retrieving a greater number of bits, including error correction information and metadata, within a single access pass without increasing latency or power consumption.
Innovation Solution
Implementing a memory device architecture with data column planes and an extra column plane for storing metadata and error correction parity bits, allowing for single-pass access of codewords, data, metadata, and ECC information by utilizing mode registers to toggle between operational modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If multiple types of information (data, metadata, ECC) are stored in the memory array, then the information retrieval capability is improved, but the access latency increases due to requiring multiple access passes
Solution Approach 1:
The memory array is segmented into multiple independent column planes (first column plane, second column plane, third column plane) that can be accessed simultaneously. Data bits are distributed across different column planes, allowing parallel retrieval of multiple data types in a single access pass, thereby reducing latency while maintaining comprehensive information retrieval capability.
Solution Approach 2:
The patent introduces a spatial dimension solution by organizing memory into multiple column planes that can be activated simultaneously. Instead of sequentially accessing different memory regions for different information types, the system uses parallel column plane activation to retrieve data, metadata, and ECC information concurrently from different spatial locations within the same memory array.
2Loss of information
If multiple types of information (data, metadata, ECC) are stored in the memory array, then the information retrieval capability is improved, but the power consumption increases due to activating more column planes
Solution Approach 1:
The patent implements local quality by allowing selective activation of only the specific column planes needed for each access operation. Rather than activating all column planes simultaneously, the system activates only those containing the required information (data, metadata, or ECC), thereby reducing power consumption while maintaining full information retrieval capability when needed.
Solution Approach 2:
The memory access system dynamically configures which column planes are activated based on the specific access requirements. The column plane selection is flexible and adaptive, enabling the system to optimize power consumption by activating only the necessary subset of column planes for each operation while maintaining the capability to retrieve all types of information when required.
3Device complexity
If traditional memory architecture is used without extra column plane, then the device complexity is low, but the ability to store and access metadata and ECC information simultaneously with data is limited
Solution Approach 1:
The patent implements universality by designing column planes that can serve multiple functions. The same memory array structure supports storage and simultaneous access of different information types (data, metadata, ECC) by distributing them across different column planes. This multi-functional architecture enables versatile access patterns without requiring separate dedicated storage regions for each information type.
Data Source
AI summary
Apparatuses, systems, and methods for single-pass access of ECC information, metadata information, or combinations thereof. The memory array includes a number of column planes and an extra column plane. A memory device may be set in an ×4 single-pass operational mode. In this mode, the memory may store data in a selected ones of the column planes, and metadata may be stored in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.